Intel Arria 10 User Manual page 81

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Name
rx_enh_fifo_align_cl
r[<n>-1:0]
Table 53. Interlaken Frame Generator, Synchronizer, and CRC32
Name
tx_enh_frame[<n>-1:0]
tx_enh_frame_diag_stat
us[<n> 2-1:0]
tx_enh_frame_burst_en[
<n>-1:0]
rx_enh_frame[<n>-1:0]
rx_enh_frame_lock[<n>-
1:0]
rx_enh_frame_diag_stat
us[2 <n>-1:0]
rx_enh_crc32_err[<n>-1
:0]
Direction Clock Domain
the FIFO
rx_coreclkin
or
rx_clkout
Input Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or
rx_clkout
Direction Clock Domain
Output
tx_clkout
Input
tx_clkout
Input
tx_clkout
Output
rx_clkout
Output
rx_clkout
Output
rx_clkout
Output
rx_clkout
Description
When asserted, the FIFO resets and begins searching
for a new alignment pattern. This signal is only valid
for the Interlaken protocol. Assert this signal for at
least 4 cycles.
Description
Asserted for 2 or 3 parallel clock cycles to indicate the
beginning of a new metaframe.
Drives the lane status message contained in the framing
layer diagnostic word (bits[33:32]). This message is
inserted into the next diagnostic word generated by the
frame generator block. This bus must be held constant for 5
clock cycles before and after the
following encodings are defined:
• Bit[1]: When 1, indicates the lane is operational. When
0, indicates the lane is not operational.
• Bit[0]: When 1, indicates the link is operational. When
0, indicates the link is not operational.
If Enable frame burst is enabled, this port controls frame
generator data reads from the TX FIFO to the frame
generator. It is latched once at the beginning of each
Metaframe. If the value of
tx_enh_frame_burst_en
the frame generator does not read data from the TX FIFO
for current Metaframe. Instead, the frame generator inserts
SKIP words as the payload of Metaframe. When
is 1, the frame generator reads
tx_enh_frame_burst_en
data from the TX FIFO for the current Metaframe. This port
must be held constant for 5 clock cycles before and after
the pulse.
tx_enh_frame
When asserted, indicates the beginning of a new received
Metaframe. This signal is pulse stretched.
When asserted, indicates the Frame Synchronizer state
machine has achieved Metaframe delineation. This signal is
pulse stretched.
Drives the lane status message contained in the framing
layer diagnostic word (bits[33:32]). This signal is latched
when a valid diagnostic word is received in the end of the
Metaframe while the frame is locked. The following
encodings are defined:
• Bit[1]: When 1, indicates the lane is operational. When
0, indicates the lane is not operational.
• Bit[0]: When 1, indicates the link is operational. When
0, indicates the link is not operational.
When asserted, indicates a CRC error in the current
Metaframe. Asserted at the end of current Metaframe. This
signal gets asserted for 2 or 3 cycles.
® ®
Intel Arria
pulse. The
tx_enh_frame
is 0,
10 Transceiver PHY User Guide
81