Intel Arria 10 User Manual page 315

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Related Information
• Arria 10 Standard PCS Architecture
For more information about Standard PCS architecture
• Arria 10 PMA Architecture
For more information about PMA architecture
• Using PLLs and Clock Networks
For more information about implementing PLLs and clocks
• PLLs
PLL architecture and implementation details
• Resetting Transceiver Channels
Reset controller general information and implementation details
• Standard PCS Ports
Port definitions for the Transceiver Native PHY Standard Datapath
2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match
Configurations
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
Table 217. General and Datapath Options Parameters
Message level for rule violations
Transceiver configuration rules
PMA configuration rules
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Table 218. TX PMA Parameters
TX channel bonding mode
PCS TX channel bonding master
Actual PCS TX channel bonding master
on page 447
on page 349
on page 86
Parameter
Parameter
on page 479
on page 398
on page 416
Basic/Custom (Standard PCS)
Basic/Custom w/Rate Match (Standard
PMA and PCS bonding
Auto, n-1 (where n = the number of data
n-1 (where n = the number of data channels)
®
Intel Arria
Range
error
warning
PCS)
basic
TX/RX Duplex
TX Simplex
RX Simplex
to
1 96
Mbps to Gbps
611 12
On/Off
On/Off
Range
Not bonded
PMA-only bonding
channels)
continued...
®
10 Transceiver PHY User Guide
315