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2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Document
Version
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Made the following changes to the "XAUI PHY IP Core Registers" table.
— Removed
— Removed
— Removed Word Addresses 0x082, 0x083, 0x086, 0x087, 0x088, 0x089
— Removed
— Changed the description for
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Added the
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Added the
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Added the "XAUI PHY Timing Analyzer SDC Constraint" section.
Made the following changes to the PCI Express section:
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Added PIPE Gen3 32 bit PCS Clock Rates table in the Gen3 Rate Switchsection.
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Updated the Rate Switch Change figure.
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Updated the Bit Mappings When the Simplified Interface Is Disabledtable.
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Updated the figures in How to Place Channels for PIPE Configurations.
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Updated the Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA
table.
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Updated the clock domains in Signals and Ports of Native PHY IP for PIPE figure.
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Updated the Ports for Arria 10 Transceiver Native PHY in PIPE Mode table.
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Updated Logical PCS Master Channel for PIPE Configuration table.
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Updated the PCIe Reverse Parallel Loopback in Gen1/Gen2 features with input signal name.
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Updated the Rate Switch Change figure.
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Updated the Gearbox Gen3 Transmission signals in the Gen3 Data Transmission figure.
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Updated the PIPE Design Example section.
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Updated the Gen3 Power State Management P1 to P0 Transition signals.
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Updated the Supported Features for PIPE Configurations table.
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Updated the Gen1/Gen2 Features section.
Made the following changes to the CPRI section:
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Updated the parameter values for "RX word aligner mode".
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Added a new option for Interlaken in the GUI "Enable Interlaken TX random disparity bit".
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For PMA configuration rules changed the option "SATA" to "SATA/SAS".
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Changed the GUI option "CTLE adaptation mode" to "DFE adaptation mode".
Made the following changes to the Other Protocols section:
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Added four new sections: "TX Bit Slip", "TX Polarity Inversion", "RX Bit Slip", and "RX Polarity
Inversion".
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Changed the initial value of
Width is 10 Bits" and "Manual Mode when the PCS-PMA Interface Width is 16 Bits" figures.
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Changed the minimum value for the "Data rate" parameter to 1 Gbps in the "General and Datapath
Options Parameters" table.
Made the following changes to the Simulating the Native Transceiver PHY section:
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In the introductory section, removed the third bullet in the list of netlists you can simulate because
gate-level timing simulation is no longer supported.
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Removed mention of the ModelSim DE simulator in the "How to Use NativeLink to Specify a
ModelSim Simulation" section.
2014.10.08
Made the following changes to the Ethernet section:
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Changed the frequency for
Version10GBASE-KR PHY IP Core with FEC Option and for 1G/10 Gbps Ethernet PHY IP Core.
Made the following changes to the Other Protocols section:
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Removed an erroneous note regarding Quartus II software legality check restrictions.
2014.08.15
Made the following changes to the Transceiver Design Flow section:
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Added "Make Pin Assignments Using Pin Planner and Assignment Editor" block to figure "Transceiver
Design Flow"
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Updated Select and Instantiate PHY IP, Generate PHY IP, Select and Instantiate PLL IP, and
Generate PLL IP sections to indicate the new IP instantiation flow per ACDS 14.0A10 release.
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Added a new section for Make Pin Assignments Using Pin Planner and Assignment Editor
cal_blk_powerdown
pma_tx_pll_is_locked
patterndetect[7:0]
syncstatus [7:0]
port to the "SDR RX XGMII Interface " table.
xgmii_rx_inclk
port to the "PMA Channel Controller Signals" table.
pll_cal_busy_i
tx_parallel_data
in the "Avalon-MM Interface Signals" table for Document
mgmt_clk
Changes
in the "Manual Mode when the PCS-PMA Interface
®
®
Intel
Arria
10 Transceiver PHY User Guide
continued...
343
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