Intel Arria 10 User Manual page 572

Rules to Build Customized Gating Logic to Separate tx_cal_busy and
rx_cal_busy signals
Figure 281. An Example of an AND Gate used as Customized Logic
The customized gates shown in the following figure are an example and not a unique solution
JTAG to
Avalon
Master
Bridge
The capability register is not available for merging a Simplex TX and a Simplex RX
signal into the same physical channel. The
rx_cal_busy_out
gating logic to separate them.
•
The
tx_cal_busy_out_en
•
The
rx_cal_busy_out_en
•
At power up,
"1".
• At normal operation:
— When the RX is calibrating, setting
rx_cal_busy_out_en
while RX is calibrating.
— When the TX is calibrating, setting
tx_cal_busy_out_en
reset while TX is calibrating.
Table 300. PMA Capability Registers for Calibration Status
Bit
0x281[5]
0x281[4]
0x281[2]
® ®
Intel Arria 10 Transceiver PHY User Guide
572
reset
Simplex
TX
tx/rx_cal_busy_out
Simplex
RX
reset
signals share the same port. So, you should build customized
signal enables the
signal enables the
tx_cal_busy_out_en
to "1" disables tx_cal_busy, so the TX does not reset
to "1" disables
PMA channel
rx_cal_busy
0x1: The
rx_cal_busy
or RX calibration is running.
0x0: The
rx_cal_busy
PMA channel
tx_cal_busy
0x1: The
tx_cal_busy
or RX calibration is running.
0x0: The
tx_cal_busy
PreSICE Avalon-MM interface control. This register is available to check who
controls the bus, no matter if, separate
of AVMM arbitration with PreSICE is enabled or not.
0x1: PreSICE is controlling the internal configuration bus.
Customized Gates
tx_cal_busy_out_en
rx_cal_busy_out_en
tx_cal_busy_out
tx_cal_busy
rx_cal_busy
and
rx_cal_busy_out_en
tx_cal_busy_out_en
rx_cal_busy_out_en
, so the RX does not
rx_cal_busy
Description
output enable. The power up default value is 0x1.
output and 0x281[1] are asserted high whenever PMA TX
output or 0x281[1] is never asserted high.
output enable. The power up default value is 0x1.
output and 0x281[0] are asserted high whenever PMA TX
output or 0x281[0] is never asserted high.
reconfig_waitrequest
7. Calibration
UG-01143 | 2018.06.15
tx_cal_busy Reset
Controller
reset
rx_cal_busy Reset reset
Contoller
and
output.
output.
should be set to
to "0" and
to "0" and
from the status
continued...