Intel Arria 10 User Manual page 287

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Table 207. RX PMA Parameters
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
DFE adaptation mode
Number of fixed dfe taps
Enable rx_pma_clkout port
Enable rx_pma_div_clkout port
rx_pma_div_clkout division factor
Enable rx_pma_clkslip port
Enable rx_pma_qpipulldn port (QPI)
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_seriallpbken port
Enable PRBS verifier control and status ports
Table 208. Standard PCS Parameters
Standard PCS / PMA interface width
FPGA fabric / Standard TX PCS interface width
FPGA fabric / Standard RX PCS interface width
Enable 'Standard PCS' low latency mode
TX FIFO mode
RX FIFO mode
Enable tx_std_pcfifo_full port
Enable tx_std_pcfifo_empty port
Enable rx_std_pcfifo_full port
Enable rx_std_pcfifo_empty port
TX byte serializer mode
RX byte deserializer mode
Enable TX 8B/10B encoder
Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
Parameter
Parameters
Value
1
0
Select legal range defined by the Quartus Prime
software
1000
manual
disabled
3
Off
On
2
Off
Off
On
On
Off
Off
Off
Value
20
32
32
Off
register_fifo
register_fifo
Off
Off
Off
Off
Serialize x2
Deserialize x2
On
Off
On
® ®
Intel Arria 10 Transceiver PHY User Guide
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