Intel Arria 10 User Manual page 23

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1. Arria 10 Transceiver PHY Overview
UG-01143 | 2018.06.15
Figure 14. GT Transceiver Bank Architecture
In the GT device, the transceiver banks GXBL1E, GXBL1G, and GXBL1H include GT channels.
Note: This figure is a high level overview of the transceiver bank architecture. For details
about the available clock networks refer to the PLLs and Clock Networks chapter.
Six-Channel GT Transceiver Bank GXBL1G
CH5
PMA PCS
Channel PLL
(CDR Only) Local CGB5
CH4
PMA
PCS
Channel PLL
Local CGB4
(CMU/CDR)
CH3
PMA
PCS
Channel PLL
Local CGB3
(CDR Only)
CH2
PMA
PCS
Channel PLL
Local CGB2
(CDR Only)
CH1
PMA
PCS
Channel PLL
Local CGB1
(CMU/CDR)
CH0
PMA
PCS
Channel PLL
Local CGB0
(CDR Only)
Legend
GX Channel
GT/GX Channel
Clock
Distribution
Network
fPLL1
Master
CGB1
FPGA Core
ATX
PLL1
fPLL0
Master
CGB0
ATX
PLL0
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Intel Arria 10 Transceiver PHY User Guide
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