Intel Arria 10 User Manual page 143

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
2.6.3.5. 10GBASE-KR PHY Interfaces
Figure 70. 10GBASE-KR Top-Level Signals
XGMII
Interfaces
Avalon-MM PHY
Management
Interface
Clocks and
Reset
Interface
The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used in
the _hw.tcl file. If you turn on Show signals, the block diagram displays all top-
level signal names.
Related Information
Component Interface Tcl Reference
For more information about _hw.tcl files
2.6.3.5.1. Clock and Reset Interfaces
Table 114. Clock and Reset Signals
Signal Name
tx_serial_clk_10g
tx_serial_clk_1g
rx_cdr_ref_clk_10g
rx_cdr_ref_clk_1g
10GBASE-KR Top-Level Ports
xgmii_tx_dc[71:0]
xgmii_tx_clk
xgmii_rx_dc[71:0]
xgmii_rx_clk
mgmt_clk
mgmt_clk_reset
mgmt_address[10:0]
mgmt_writedata[31:0]
mgmt_readdata[31:0]
mgmt_write
mgmt_read
mgmt_waitrequest
tx_serial_clk_10g
rx_cdr_ref_clk_10g
tx_pma_clkout
rx_pma_clkout
tx_clkout
rx_clkout
tx_pma_div_clkout
rx_pma_div_clkout
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
usr_seq_reset
Direction
Input High speed clock from the 10G PLL to drive 10G PHY TX PMA. The
frequency of this clock is 5.15625 GHz.
Input High speed clock from 1G PLL to drive the 1G PHY TX PMA. This clock
is not required if GbE is not used. The frequency of this clock is 625
MHz.
Input 10G PHY RX PLL reference clock. This clock frequency can be
644.53125 MHz or 322.2656 MHz.
Input 1G PHY RX PLL reference clock. The frequency is 125 MHz. This clock
is only required if 1G is enabled.
rx_serial_data
tx_serial_data
rx_block_lock
rx_hi_ber
rx_is_lockedtodata
tx_cal_busy
rx_cal_busy
rx_syncstatus
lcl_rf
rx_clkslip
rx_latency_adj_10g[11:0]
tx_latency_adj_10g[11:0]
rx_data_ready
Description
® ®
Intel Arria 10 Transceiver PHY User Guide
Transceiver
Serial Data
Status
continued...
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