Intel Arria 10 User Manual page 212

Signal Name
xgmii_tx_valid
RX XGMII signals—synchronous to
xgmii_rx_data
xgmii_rx_control
xgmii_rx_valid
® ®
Intel Arria 10 Transceiver PHY User Guide
212
Direction Width
Output 1
xgmii_rx_coreclkin
Output 64, 32
Output 8, 4
Output 1
2. Implementing Protocols in Arria 10 Transceivers
Description
• 8 bits for 1G/2.5G/10G configurations.
• 4 bits for 1G/2.5G/5G/10G configurations.
Indicates valid data on
xgmii_tx_control
from the MAC.
xgmii_tx_data
Your logic/MAC must toggle the valid data as
shown below:
Speed
1G
2.5G
5G
10G
RX data to the MAC. The PHY sends the data in the
following order: bits[7:0], bits[15:8], and so forth.
The width is:
• 64 bits for 1G/2.5G/10G configurations.
• 32 bits for 1G/2.5G/5G/10G configurations.
RX control to the MAC.
•
[0] corresponds to
xgmii_rx_control
[7:0]
xgmii_rx_data
•
[1] corresponds to
xgmii_rx_control
[15:8]
xgmii_rx_data
• and so forth.
The width is:
• 8 bits for 1G/2.5G/10G configurations.
• 4 bits for 1G/2.5G/5G/10G configurations.
Indicates valid data on
xgmii_rx_control
from the MAC.
xgmii_rx_data
The toggle rate from the PHY is shown in the table
below.
Note: The toggle rate may vary when the start of
a packet is received or when rate match
occurs inside the PHY. You should not
expect the valid data pattern to be fixed.
Speed
1G
2.5G
5G
10G
UG-01143 | 2018.06.15
and
Toggle Rate
Asserted once every 10
clock cycles
Asserted once every 4
clock cycles
Asserted once every 2
clock cycles
Always asserted
and
Toggle Rate
Asserted once every 10
clock cycles
Asserted once every 4
clock cycles
Asserted once every 2
clock cycles
Always asserted