Intel Arria 10 User Manual page 87

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
In the following tables, the variables represent these parameters:
• <n>—The number of lanes
• <w>—The width of the interface
• <d>—The serialization factor
• <s>— The symbol size
• <p>—The number of PLLs
Table 68. TX Standard PCS: Data, Control, and Clocks
Name
tx_parallel_data[<n>
128-1:0]
unused_tx_parallel_d
ata
tx_coreclkin
tx_clkout
Table 69. RX Standard PCS: Data, Control, Status, and Clocks
Name
rx_parallel_data[<n>
128-1:0]
unused_rx_parallel_da
ta
rx_clkout
rx_coreclkin
Direction Clock Domain
Input
tx_clkout
Input
tx_clkout
Input Clock
Output Clock
Direction Clock Domain
Output Synchronous
to the clock
driving the
read side of
the FIFO
(
rx_coreclk
or
in
)
rx_clkout
Output Synchronous
to the clock
driving the
read side of
the FIFO
(
rx_coreclk
or
in
)
rx_clkout
Output Clock
Input Clock
Description
TX parallel data input from the FPGA fabric to the TX PCS.
This signal specifies the unused data when you turn on
Enable simplified data interface. When simplified data
interface is not set, the unused bits are a part of
. Connect all these bits to 0. If you do
tx_parallel_data
not connect the unused data bits to 0, then TX parallel data
may not be serialized correctly by the Native PHY IP core.
The FPGA fabric clock. This clock drives the write port of the
TX FIFO.
This is the parallel clock generated by the local CGB for non
bonded configurations, and master CGB for bonded
configuration. This clocks the
FPGA fabric to the TX PCS.
Description
RX parallel data from the RX PCS to the FPGA fabric. For
each 128-bit word of
rx_parallel_data
correspond to
rx_parallel_data[7:0]
decoder is enabled and
rx_parallel_data[9:0]
8B/10B decoder is disabled.
This signal specifies the unused data when you turn on
Enable simplified data interface. When simplified data
interface is not set, the unused bits are a part of
. These outputs can be left floating.
rx_parallel_data
The low speed parallel clock recovered by the transceiver RX
PMA, that clocks the blocks in the RX Standard PCS.
RX parallel clock that drives the read side clock of the RX
FIFO.
®
Intel Arria
from the
tx_parallel_data
, the data bits
when 8B/10B
when
®
10 Transceiver PHY User Guide
87