Intel Arria 10 User Manual page 132

2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE
1588v2, and 10GBASE-R with FEC
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
Table 95. General and Datapath Parameters
The first two sections of the Transceiver Native PHY parameter editor provide a list of general and datapath
options to customize the transceiver.
Message level for rule violations
Transceiver Configuration Rule
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Table 96. TX PMA Parameters
TX channel bonding mode
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Table 97. RX PMA Parameters
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
DFE adaptation mode
Number of fixed DFE taps
(35)
The CDR reference clock frequency depends on your design settings. Intel recommends that
you verify the link datarates to ensure the CDR locking capability before production.
® ®
Intel Arria 10 Transceiver PHY User Guide
132
Parameter
Parameter
Parameter
(35)
2. Implementing Protocols in Arria 10 Transceivers
Range
error, warning
10GBASE-R
10GBASE-R 1588
10GBASE-R with KR FEC
TX / RX Duplex, TX Simplex, RX Simplex
1 to 96
10312.5 Mbps
Off
On
Off
Range
Not bonded
1, 2, 4, 8
1, 2, 3, 4
0
Range
1 to 5
0 to 4
156.25 MHz, 322.265625 MHz, and 644.53125 MHz
100, 300, 500, 1000
manual
adaptation enabled, manual, disabled
3, 7, 11
UG-01143 | 2018.06.15