Intel Arria 10 User Manual page 484

Related Information
Refer to Specifications & Additional Information for more information about 8B/10B
encoder codes.
5.3.1.3.2. 8B/10B Encoder Reset Condition
The
tx_digitalreset
the 8B/10B encoder outputs K28.5 continuously until
5.3.1.3.3. 8B/10B Encoder Idle Character Replacement Feature
The idle character replacement feature is used in protocols such as Gigabit Ethernet,
which requires the running disparity to be maintained during idle sequences. During
these idle sequences, the running disparity has to be maintained such that the first
byte of the next packet always starts when the running disparity of the current packet
is negative.
When an ordered set, which consists of two code-groups, is received by the 8B/10B
encoder, the second code group is converted into /I1/ or /I2 so that the final running
disparity of the data code-group is negative. The first code group is /K28.5/ and the
second code group is a data code-group other than /D21.5/ or /D2.2/. The ordered
set /I1/ (/K28.5/D5.6/) is used to flip the running disparity and /I2/ (/K28.5/D16.2/)
is used to preserve the running disparity.
5.3.1.3.4. 8B/10B Encoder Current Running Disparity Control Feature
The 8B/10B encoder performs a running disparity check on the 10-bit output data.
The running disparity can also be controlled using
When the PCS-PMA interface width is 10 bits,
one bit each. When the PCS-PMA interface width is 20 bits,
tx_dispval
corresponds to the LSByte of the input data and the MSB corresponds to the MSByte
of the input data.
5.3.1.3.5. 8B/10B Encoder Bit Reversal Feature
Figure 257. 8B/10B Encoder Bit Reversal Feature
7
The bit reversal feature reverses the order of the bits of the input data. Bit reversal is
performed at the output of the 8B/10B Encoder and is available even when the
8B/10B Encoder is disabled. For example, if the input data is 20-bits wide, bit reversal
switches bit [0] with bit [19], bit [1] with bit [18] and so on.
® ®
Intel Arria 10 Transceiver PHY User Guide
484
signal resets the 8B/10B encoder. During the reset condition,
are two bits each. The LSB of
Output
Data
0
5. Arria 10 Transceiver PHY Architecture
tx_digitalreset
tx_forcedisp
tx_forcedisp
tx_forcedisp
and
tx_forcedisp
Input
Bit Reversal Mode
Data
(8B/10B Encoder)
UG-01143 | 2018.06.15
goes low.
and .
tx_dispval
and are
tx_dispval
and
tx_dispval
0 7