Intel Arria 10 User Manual page 263

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Port
pipe_sw[1:0]
Table 191. Bit Mappings When the Simplified Interface Is Disabled
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter values.
Signal Name
tx_parallel_data
tx_datak
pipe_tx_compliance
pipe_tx_elecidle
pipe_tx_detectrx_loop
bacK
pipe_powerdown
pipe_tx_margin
pipe_tx_swing
rx_parallel_data
rx_datak
rx_syncstatus
pipe_phy_status
pipe_rx_valid
pipe_rx_status
Direction Clock Domain
Out N/A
Gen1 (TX Byte Gen1 (TX Byte
Serializer and RX Serializer and RX Byte
Byte Deserializer Deserializer in X2
disabled) mode), Gen2 (TX Byte
Serializer and RX Byte
Deserializer in X2
tx_parallel_dat tx_parallel_data[29
a[7:0] :22,7:0]
tx_parallel_dat tx_parallel_data[30
a[8] ,8]
tx_parallel_dat tx_parallel_data[31
a[9] ,9]
tx_parallel_dat tx_parallel_data[32
a[10] ,10]
tx_parallel_dat tx_parallel_data[46
a[46] ]
tx_parallel_dat tx_parallel_data[48
a[48:47] :47]
tx_parallel_dat tx_parallel_data[51
a[51:49] :49]
tx_parallel_dat tx_parallel_data[53
a[53] ]
rx_parallel_dat rx_parallel_data[39
a[7:0] :32,7:0]
rx_parallel_dat rx_parallel_data[40
a[8] ,8]
rx_parallel_dat rx_parallel_data[42
a[10] ,10]
rx_parallel_dat rx_parallel_data[65
a[65] ]
rx_parallel_dat rx_parallel_data[66
a[66] ]
rx_parallel_dat rx_parallel_data[69
a[69:67] :67]
3'b111 - Receive disparity error, not used if
disparity error is reported using 3'b100.
Signal to clock generation buffer indicating
the rate switch request. Use this signal for
bonding mode only.
For non-bonded applications this signal is
internally connected to the local CGB.
Active High. Refer to
Bit Mappings When the Simplified Interface is
Disabled for more details.
mode)
tx_parallel_data[40:33,29:22,18
:11,7:0]
tx_parallel_data[41,30,19,8]
tx_parallel_data[42,31,20,9]
tx_parallel_data[43,32,21,10]
tx_parallel_data[46]
tx_parallel_data[48:47]
tx_parallel_data[51:49]
tx_parallel_data[53]
rx_parallel_data[55:48,39:32,23
:16,7:0]
rx_parallel_data[56,40,24,8]
rx_parallel_data[58,42,26,10]
rx_parallel_data[65]
rx_parallel_data[66]
rx_parallel_data[69:67]
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Intel Arria
Description
Table 191 on page 263
Gen3
continued...
10 Transceiver PHY User Guide
263