Intel Arria 10 User Manual page 168

Related Information
• Arria 10 Enhanced PCS Architecture
• Arria 10 Standard PCS Architecture
• Arria 10 PMA Architecture
• 10-Gbps Ethernet MAC IP Function User Guide.
For more information about latency in the MAC as part of the Precision Time
Protocol implementation.
2.6.4.4. Clock and Reset Interfaces
You can use a fPLL or a CMU PLL to generate the clock for the TX PMA for the 1G data
rate. For the 10G data rate, you can use the ATX PLL or the CMU PLL. For the 1G data
rate, the frequency of the TX and RX clocks is 125 MHz, which is 1/8 of the MAC data
rate. For the 10G data rate, the frequency of TX and RX clocks is 156.25 MHz, 1/64 of
the MAC data rate. You can generate the 156.25 MHz clock directly by using a fPLL, or
you can divide the clock from TX PLL by 33. The 1G/10GbE PHY does not support
bonded clocks.
The following figure provides an overview of the clocking for this core.
Figure 75. Clocks for Standard and 10G PCS and TX PLLs
red = datapath includes FEC
Notes:
1. 257.8125 MHz is for 10GbE.
2. 161.1 MHz is the FEC clock for 10GbE.
The following table describes the clock and reset signals.
® ®
Intel Arria 10 Transceiver PHY User Guide
168
on page 447
1GbE/10GbE PHY
GMII TX
Data & Control
SGMII
PCS
tx_coreclkin_1g
125 MHz
64 + 8
XGMII TX Data & Control
fractional
64 + 8
xgmii_tx_clk
PLL
156.25 MHz
(instantiate
separately)
GMII RX
Data & Control
SGMII
PCS
rx_pld_clk
rx_coreclkin_1g
125 MHz
64 + 8
XGMII RX Data & Control
xgmii_rx_clk
156.25 MHz
2. Implementing Protocols in Arria 10 Transceivers
on page 461
on page 479
TX data
10
8+1
Standard TX PCS
tx_pld_clk tx_pma_clk
40
64
tx_pld_clk
TX data
Enhanced TX PCS
tx_pld_clk tx_pma_clk
8+1
10
Standard RX PCS
rx_pma_clk
Enhanced RX PCS 60
64 + 8
40
rx_pld_clk rx_pma_clk
UG-01143 | 2018.06.15
TX serial data
TX PMA
pll_ref_clk_1g
TX PLL
125 MHz
pll_ref_clk_10g
TX PLL
644.53125 MHz
or
322.265625 MHz
RX data
RX PMA
serial data
recovered clk
125 MHz
257.8125 MHz (1)
161.1 MHz (2)