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2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Figure 43.
Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with
IEEE 1588v2
625 MHz
625 MHz
Notes:
1. This block is set in low latency mode for GbE and register_fifo mode for GbE with IEEE 1588v2.
2. The rate match FIFO of the hard PCS is disabled for GbE with IEEE 1588v2 because it is not able to acheive deterministic latency. It is also disabled for Triple-speed Ethernet (TSE) configurations that require an auto-negotiation sequency.
The insertion/deletion operation could break the auto-negotiation functionality due to the rate matching of different frequency PPM scenarios.The soft rate match FIFO is constructed in the GbE Serial Gigabit Media Independent Interface
(SGMII) IP core.
3. The byte serializer can be enabled or disabled.
4. The byte deserializer can be enabled or disabled.
5. The CGB is in the Native PHY.
Note:
The Native PHY only supports basic PCS functions. The Native PHY does not support
auto-negotiation state machine, collision-detect, and carrier-sense. If required, you
must implement these functions in the FPGA fabric or external circuits.
GbE with IEEE 1588v2
GbE with IEEE 1588v2 provides a standard method to synchronize devices on a
network with submicrosecond precision. To improve performance, the protocol
synchronizes slave clocks to a master clock so that events and time stamps are
synchronized in all devices. The protocol enables heterogeneous systems that include
clocks of various inherent precision, resolution, and stability to synchronize to a
grandmaster clock.
The TX FIFO and RX FIFO are set to register_fifo mode for GbE with IEEE 1588v2.
Related Information
Triple-Speed Ethernet IP Function User Guide.
For more information about the IEEE 1588v2 implementation in GbE PHY and MAC,
and design examples.
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2
The 8B/10B encoder clocks 8-bit data and 1-bit control identifiers from the transmitter
phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded
data is sent to the PMA.
Transmitter PMA
10
125 MHz
tx_clkout
tx_pma_div_clkout
Receiver PMA
10
Parallel Clock
rx_clkout
(Recovered)
125 MHz
tx_clkout
Parallel Clock
(From Clock
PRBS
Divider)
Verifier
Parallel Clock
Serial Clock
Parallel and Serial Clock
Transmitter Standard PCS
PRBS
Generator
/2
Receiver Standard PCS
/2
rx_pma_div_clkout
Clock Generation Block (CGB) (5)
Clock Divider
Parallel and Serial Clock
®
®
Intel
Arria
FPGA
Fabric
8
tx_coreclkin
125 MHz
tx_clkout
8
rx_coreclkin
125 MHz
rx_clkout or
tx_clkout
ATX PLL
CMU PLL
fPLL
Serial Clock
10 Transceiver PHY User Guide
113
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