Intel Arria 10 User Manual page 133

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Table 98. Enhanced PCS Parameters
Enhanced PCS/PMA interface width
FPGA fabric/Enhanced PCS interface width
Enable Enhanced PCS low latency mode
Enable RX/TX FIFO double-width mode
TX FIFO mode
TX FIFO partially full threshold
TX FIFO partially empty threshold
RX FIFO mode
RX FIFO partially full threshold
RX FIFO partially empty threshold
Table 99. 64B/66B Encoder and Decoder Parameters
Enable TX 64B/66B encoder
Enable RX 64B/66B decoder
Enable TX sync header error insertion
Table 100. Scrambler and Descrambler Parameters
Enable TX scrambler (10GBASE-R / Interlaken)
TX scrambler seed (10GBASE-R / Interlaken)
Enable RX descrambler (10GBASE-R / Interlaken)
Table 101. Block Sync Parameters
Enable RX block synchronizer
Enable rx_enh_blk_lock port
Table 102. Gearbox Parameters
Enable TX data polarity inversion
Enable RX data polarity inversion
Parameter
Parameter
Parameter
Parameter
Parameter
Range
32, 40, 64
Note: 10GBASE-R with KR-FEC allows 64 only.
66
On
Off
Off
• Phase Compensation (10GBASE-R and 10GBASE-R
with KR FEC)
• Register or Fast register (10GBASE-R with 1588)
11
2
• 10GBASE-R (10GBASE-R and 10GBASE-R with KR FEC)
• Register (10GBASE-R with 1588)
23
2
Range
On
On
On
Off
Range
On
0x03ffffffffffffff
On
Range
On
On
Off
Range
On
Off
On
Off
® ®
Intel Arria 10 Transceiver PHY User Guide
133