Intel Arria 10 User Manual page 385

3. PLLs and Clock Networks
UG-01143 | 2018.06.15
networks in the FPGA core. If the Global Signal is set to Off, it does not choose any of
the previously mentioned clock networks. Instead, it chooses directly from the local
routing between transceiver and FPGA fabric.
The transmitter channel forwards a parallel output clock
fabric to clock the transmitter data and control signals. The receiver channel forwards
a parallel output clock
signals from the receiver into the FPGA fabric. Based on the receiver channel
configuration, the parallel output clock is recovered from either the receiver serial data
or the
rx_clkout
tx_clkout
Figure 180. FPGA Fabric - Transceiver Interface Clocking
Parallel Clock
The divided versions of the
tx_pma_div_clkout
rx_clkout
clock (in configurations without the rate matcher) or the
clock (in configurations with the rate matcher).
Transmitter PMA Transmitter Standard PCS
tx_clkout
tx_pma_div_clkout
Receiver PMA Receiver Standard PCS
Parallel Clock
(Recovered) rx_clkout
tx_clkout
(From Clock PRBS
Divider) Verifier
Serializer
/66
/40
/33
/2
tx_pma_div_clkout
Deserializer
/66
/40
/33
/2
rx_pma_div_clkout
tx_clkout
and
rx_pma_div_clkout
to the FPGA fabric to clock the data and status
PRBS
Generator
/2, /4
/2, /4
rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
Serial Clock tx_clkout
(from CGB)
CDR Recovered
Clock
rx_clkout
and
rx_clkout
, respectively.
Intel
to the FPGA
tx_clkout
FPGA
Fabric
tx_coreclkin
tx_clkout
rx_coreclkin
rx_clkout or
tx_clkout
CMU PLL /
ATX PLL /
fPLL
Serial Clock
Parallel and Serial Clocks
Input Reference Clock
Parallel Clock
Serial Clock
Parallel and Serial Clocks
are available as
® ®
Arria 10 Transceiver PHY User Guide
385