Intel Arria 10 User Manual page 104

Figure 38. Signals and Ports of Native PHY IP for Interlaken
tx_bonding_clocks[5:0]
Notes:
(1) The width of tx_parallel_data and tx_control depends on whether the simplified interface is enabled or not. If the simplified interface is enabled, then
(2) The width of rx_parallel_data and rx_control depends on whether the simplified interface is enabled or not. If the simplified interface is enabled, then
5. Configure and instantiate your PLL.
6. Create a transceiver reset controller. You can use your own reset controller or use
the Transceiver PHY Reset Controller.
7. Implement a TX soft bonding logic and an RX multi-lane alignment deskew state
machine using fabric logic resources for multi-lane Interlaken implementation.
8. Connect the Native PHY IP to the PLL IP and the reset controller.
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Intel Arria 10 Transceiver PHY User Guide
104
tx_cal_busy Hard
rx_cal_busy Calibration Block
TX PMA
tx_serial_data
Serializer
tx_serial_clk or
(from TX PLL)
RX PMA
rx_serialloopback
rx_serial_data
CDR
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
tx_parallel_data = 64 bits and tx_control = 3 bits. The width shown here is without simplified interface.
rx_parallel_data = 64 bits and rx_control = 10 bits. The width shown here is without simplified interface.
2. Implementing Protocols in Arria 10 Transceivers
Arria 10 Transceiver Native PHY
Reconfiguration
Registers
TX Enhanced PCS
32/40/64
RX Enhanced PCS
32/40/64
Deserializer
UG-01143 | 2018.06.15
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digital_reset
tx_clkout
tx_coreclkin
tx_control[17:0] (1)
tx_parallel_data[127:0] (1)
tx_enh_data_valid
tx_enh_frame_burst_en
tx_enh_frame_diag_status[1:0]
tx_enh_frame
tx_enh_fifo_cnt[3:0]
tx_enh_fifo_full
tx_enh_fifo_pfull
tx_enh_fifo_empty
tx_enh_fifo_pempty
tx_analog_reset
rx_analog_reset
rx_digital_reset
rx_clkout
rx_coreclkin
rx_parallel_data[127:0] (2)
rx_control[19:0] (2)
rx_enh_fifo_rd_en
rx_enh_data_valid
rx_enh_fifo_align_val
rx_enh_fifo_align_clr
rx_enh_frame
rx_enh_fifo_cnt[3:0]
rx_enh_fifo_full
rx_enh_fifo_pfull
rx_enh_fifo_empty
rx_enh_fifo_pempty
rx_enh_frame_diag_status[1:0]
rx_enh_frame_lock
rx_enh_crc32_err
rx_enh_blk_lock