Intel Arria 10 User Manual page 237

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Note:
In Native PHY IP core - PIPE configuration, you must set
the transceiver datarate switch sequence.
2.7.2.2.2. Rate Switch
This section provides an overview of auto rate change between PIPE Gen1 (2.5 Gbps),
Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps) modes.
In Arria 10 devices, there is one ASN block common to the Standard PCS and Gen3
PCS, located in the PMA PCS interface that handles all PIPE speed changes. The PIPE
interface clock rate is adjusted to match the data throughput when a rate switch is
requested.
Table 183. PIPE Gen3 32 bit PCS Clock Rates
PCIe Gen3 Capability Mode
Enabled
Lane data rate
PCS clock frequency
FPGA fabric IP clock
frequency
PIPE interface width
pipe_rate [1:0]
Figure 97. Rate Switch Change
The block-level diagram below shows a high level connectivity between ASN and Standard PCS and Gen3 PCS.
pipe_rate[1:0]
from FPGA Fabric
pipe_phy_status
pll_pcie_clk
Gen1
2.5 Gbps
250 MHz
62.5 MHz
32-bit
2'b00
Standard PCS
PCS/PMA INF
PHYSTATUS
GEN
TX
FIFO
pipe_rate[1:0]
Gen2
5 Gbps
500 MHz
125 MHz
32-bit
2'b01
Control Plane
Bonding Up
Gen3 PCS
Gen3 ASN
(Gen1, Gen2, Gen3)
PHYSTATUS
/2
(for Gen1 Only)
Control Plane
Bonding Down
® ®
Intel Arria
to initiate
Gen3
8 Gbps
250 MHz
250 MHz
32-bit
2'b10
PMA
pipe_sw
pipe_sw_done
GEN
10 Transceiver PHY User Guide
237