Intel Arria 10 User Manual page 420

Figure 201. Transmitter and Receiver Reset Sequence
4.3.1.1.1. Resetting the Transmitter During Device Operation
Follow this reset sequence to reset the PLL or the analog or digital blocks of the
transmitter at any point during the device operation. Use this reset sequence to
reestablish a link or after dynamic reconfiguration. The following steps detail the
transmitter reset sequence during device operation. The step numbers correspond to
the numbers in the following figure.
1. Perform the following steps:
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Intel Arria 10 Transceiver PHY User Guide
420
Transmit
1 or
Receive
FPGA Device
2
Power Up/Operation
Ensure Calibration
3
Completed
PLL,TX/RX Analog
4
Reset Asserted
Wait for required time and all gating
5 conditions and release PLL/Analog
resets
Associated PLL/CDR
6
Locked
Release TX/RX
7
Digital Reset
TX/RX Reset
8
Completed
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15