Intel Arria 10 User Manual page 227

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Table 178. XAUI PHY IP Core Registers
Word Bits R/W
Addr
0x041 [31:0] RW
0x042 [1:0] W
R
0x044 [31:4,0 RW
]
[1] RW
[2] RW
[3] RW
0x061 [31:0] RW
0x064 [31:0] RW
0x065 [31:0] RW
0x066 [31:0] RO
0x067 [31:0] RO
0x084 [31:16] N/A
[15:8] R
Register Name
Reset Control Registers–Automatic Reset Controller
reset_ch_bitmask
(write)
reset_control
(read)
reset_status
Reset Controls –Manual Mode
Reserved
reset_tx_digital
reset_rx_analog
reset_rx_digital
PMA Control and Status Registers
phy_serial_loopback
pma_rx_set_locktodata
pma_rx_set_locktoref
pma_rx_is_lockedtodata
pma_rx_is_lockedtoref
XAUI PCS
Reserved
Reserved
Description
Bit mask for reset registers at addresses 0x042 and
0x044. The default value is all 1s. You can reset
channel < > when bit< > = 1.
n n
Writing a 1 to bit 0 initiates a TX digital reset using
the reset controller module. The reset affects
channels enabled in the
reset_ch_bitmask
a 1 to bit 1 initiates a RX digital reset of channels
enabled in the
reset_ch_bitmask
clears.
Reading bit 0 returns the status of the reset controller
TX ready bit. Reading bit 1 returns the status of the
reset controller RX ready bit. This bit self-clears.
It is safe to write 0s to reserved bits.
Writing a 1 causes the internal TX digital reset signal
to be asserted, resetting all channels enabled in
. You must write a 0 to clear the
reset_ch_bitmask
reset condition.
Writing a 1 causes the internal RX analog reset signal
to be asserted, resetting the RX analog logic of all
channels enabled in
reset_ch_bitmask
write a 0 to clear the reset condition.
Writing a 1 causes the RX digital reset signal to be
asserted, resetting the RX digital channels enabled in
. You must write a 0 to clear the
reset_ch_bitmask
reset condition.
Writing a 1 to channel < > puts channel <
n
serial loopback mode. For information about pre- or
post-CDR serial loopback modes, refer to Loopback
Modes.
When set, programs the RX CDR PLL to lock to the
incoming data. Bit < > corresponds to channel <
n
When set, programs the RX CDR PLL to lock to the
reference clock. Bit < > corresponds to channel <
n
When asserted, indicates that the RX CDR PLL is
locked to the RX data, and that the RX CDR has
changed from LTR to LTD mode. Bit <
to channel < >.
n
When asserted, indicates that the RX CDR PLL is
locked to the reference clock. Bit <
channel < >.
n
N/A
N/A
® ®
Intel Arria 10 Transceiver PHY User Guide
. Writing
. This bit self-
. You must
> in
n
>.
n
>.
n
> corresponds
n
> corresponds to
n
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