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Table 54.
10GBASE-R BER Checker
Name
rx_enh_highber[<n>-1:0
]
rx_enh_highber_clr_cn
t[<n>-1:0]
rx_enh_clr_errblk_coun
(10GBASE-R
t[<n>-1:0]
and FEC)
Table 55.
Block Synchronizer
Name
rx_enh_blk_lock<n>-1:0
]
Table 56.
Gearbox
Name
rx_bitslip[<n>-1:0]
tx_enh_bitslip[<n>-1:0
]
Table 57.
KR-FEC
Name
tx_enh_frame[<n>-1:0]
rx_enh_frame[<n>-1:0]
rx_enh_frame_diag_stat
us
Related Information
•
ATX PLL IP Core
•
CMU PLL IP Core
•
fPLL IP Core
•
Ports and Parameters
®
®
Intel
Arria
10 Transceiver PHY User Guide
82
Direction
Clock Domain
Output
rx_clkout
Input
rx_clkout
Input
rx_clkout
Direction
Clock Domain
Output
rx_clkout
Direction
Clock Domain
Input
rx_clkout
Input
rx_clkout
Direction
Clock Domain
Output
tx_clkout
Output
rx_clkout
Output
rx_clkout
on page 354
on page 370
on page 362
on page 535
2. Implementing Protocols in Arria 10 Transceivers
Description
When asserted, indicates a bit error rate that is greater
-4
than 10
. For the 10GBASE-R protocol, this BER rate
occurs when there are at least 16 errors within 125 µs.
This signal gets asserted for 2 to 3 clock cycles.
When asserted, clears the internal counter that indicates
the number of times the BER state machine has entered
the BER_BAD_SH state.
When asserted the error block counter resets to 0.
Assertion of this signal clears the internal counter that
counts the number of times the RX state machine has
entered the
state. In modes where the FEC block is
RX_E
enabled, the assertion of this signal resets the status
counters within the RX FEC block.
Description
When asserted, indicates that block synchronizer has
achieved block delineation. This signal is used for
10GBASE-R and Interlaken.
Description
The
slips 1 bit for every positive edge
rx_parallel_data
of the
input. Keep the minimum interval
rx_bitslip
between
pulses to at least 20 cycles. The
rx_bitslip
maximum shift is < pcswidth -1> bits, so that if the PCS is
64 bits wide, you can shift 0-63 bits.
The value of this signal controls the number of bits to slip
the
before passing to the PMA.
tx_parallel_data
Description
Asynchronous status flag output of TX KR-FEC that signifies
the beginning of generated KR FEC frame
Asynchronous status flag output of RX KR-FEC that
signifies the beginning of received KR FEC frame
Asynchronous status flag output of RX KR-FEC that
indicates the status of the current received frame.
•
00: No error
•
01: Correctable Error
•
10: Un-correctale error
•
11: Reset condition/pre-lock condition
UG-01143 | 2018.06.15
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