Intel Arria 10 User Manual page 65

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Table 35. Word Aligner and Bitslip Parameters
Parameter
Enable TX bitslip
Enable tx_std_bitslipboundarysel
port
RX word aligner mode
RX word aligner pattern length
RX word aligner pattern (hex)
Number of word alignment
patterns to achieve sync
Number of invalid words to lose
sync
Number of valid data words to
decrement error count
Enable fast sync status reporting
for deterministic Latency SM
Enable rx_std_wa_patternalign
port
Enable rx_std_wa_a1a2size port
Enable
rx_std_bitslipboundarysel port
Enable rx_bitslip port
Range
On / Off When you turn on this option, the PCS includes the bitslip
function. The outgoing TX data can be slipped by the
number of bits specified by the
tx_std_bitslipboundarysel
On / Off
Enables the
bitslip Specifies the RX word aligner mode for the Standard PCS.
The word aligned width depends on the PCS and PMA width,
manual (PLD
and whether or not 8B/10B is enabled.
controlled)
Refer to "Word Aligner" for more information.
synchronous state
machine
deterministic
latency
7, 8, 10, 16, 20, Specifies the length of the pattern the word aligner uses for
32, 40 alignment.
Refer to "RX Word Aligner Pattern Length" table in "Word
Aligner". It shows the possible values of "Rx Word Aligner
Pattern Length" in all available word aligner modes.
User-specified Specifies the word alignment pattern in hex.
Specifies the number of valid word alignment patterns that
0-255
must be received before the word aligner achieves
synchronization lock. The default is 3.
Specifies the number of invalid data codes or disparity
0-63
errors that must be received before the word aligner loses
synchronization. The default is 3.
Specifies the number of valid data codes that must be
0-255
received to decrement the error counter. If the word aligner
receives enough valid data codes to decrement the error
count to 0, the word aligner returns to synchronization lock.
On / Off
When enabled, the
immediately after the deserializer has completed slipping
the bits to achieve word alignment. When it is not selected,
rx_syncstatus
complete and the word alignment pattern is detected by the
PCS (i.e.
is only applicable when the selected protocol is CPRI (Auto).
On / Off Enables the
word aligner is configured in manual mode and when this
signal is enabled, the word aligner aligns to next incoming
word alignment pattern.
On / Off
Enables the optional
port.
On / Off
Enables the optional
output port.
On / Off
Enables the
the Standard PCS and Enhanced PCS.
Description
control signal.
tx_std_bitslipboundarysel
asserts high
rx_syncstatus
asserts after the cycle slip operation is
is asserted). This parameter
rx_patterndetect
rx_std_wa_patternalign
rx_std_wa_a1a2size
rx_std_bitslipboundarysel
port. This port is shared between
rx_bitslip
® ®
Intel Arria 10 Transceiver PHY User Guide
control signal.
port. When the
control input
status
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