Intel Arria 10 User Manual page 182

Note: Do not write to any register that is not specified.
Table 145. 1G/10GbE Register Definitions
Word Bit R/W
Addr
0x4B0 0 RW
1 RW
2 RW
3 RW
7:4 RW
8 RW
16 RW
17 RW
18 RW
0x4B1 0 R
1 R
2 R
13:8 R
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Intel Arria 10 Transceiver PHY User Guide
182
Name
When set to 1, resets the 10GBASE-KR sequencer (auto rate
Reset SEQ
detect logic), initiates a PCS reconfiguration, and may restart
Auto-Negotiation (AN), Link Training (LT), or both if AN and LT are
enabled (10GBASE-KR mode). SEQ Force Mode[2:0] forces these
modes. This reset self clears.
AN disable timer. If disabled (
Disable AN Timer
may get stuck and require software support to remove the
ABILITY_DETECT capability if the link partner does not include
this feature. In addition, software may have to take the link out of
loopback mode if the link is stuck in the ACKNOWLEDGE_DETECT
state. To enable this timer set
When set to 1, disables the Link Fail timer. When set to 0, the
Disable LF Timer
Link Fault timer is enabled.
When set to 1, the last LT measurement is a non-zero number.
fail_lt_if_ber
Treat this as a failed run. 0 = Normal.
Other than the "No force" mode (0x4B0[7:4] = 4'b0000), you
SEQ Force Mode[2:0]
must write the
required data mode by changing (forcing) the 0x4B0[7:4] bits.
The following encodings are defined:
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When set to 1, it enables the Arria 10 HSSI reconfiguration
Enable Arria 10
calibration as part of the PCS dynamic reconfiguration. 0 skips the
Calibration
calibration when the PCS is reconfigured.
When set to 1, FEC is enabled. When set to 0, FEC is disabled.
KR FEC enable 171.0
Resets to the CAPABLE_FEC parameter value.
When set to 1, KR PHY FEC decoding errors are signaled to the
KR FEC enable err
PCS. When set to 0, FEC errors are not signaled to the PCS. See
ind 171.1
Clause 74.8.3 of IEEE 802.3ap-2007 for details.
When set to 1, enables the FEC request. When this bit changes,
KR FEC request
you must assert the
with the new value. When set to 0, disables the FEC request.
When asserted, the sequencer indicates the link is ready.
SEQ Link Ready
When asserted, the sequencer has had an AN timeout. This bit is
SEQ AN timeout
latched and is reset when the sequencer restarts AN.
When set, indicates that the sequencer has had a timeout.
SEQ LT timeout
Specifies the sequencer mode for PCS reconfiguration. The
SEQ Reconfig
following modes are defined:
Mode[5:0]
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2. Implementing Protocols in Arria 10 Transceivers
Description
Disable AN Timer
Disable AN Timer = 0
(0x4B0[0]) to 1 when switching to the
Reset SEQ
0000: No force
0001: GbE
0010: XAUI
0100: 10GBASE-R
0101: 10GBASE-KR
1100: 10GBASE-KR FEC
Reset SEQ
Bit 8, mode[0]: AN mode
Bit 9, mode[1]: LT Mode
Bit 10, mode[2]: 10G data mode
Bit 11, mode[3]: GbE data mode
Bit 12, mode[4]: Reserved for XAUI
Bit13, mode[5]: 10G FEC mode
UG-01143 | 2018.06.15
= 1) , AN
.
bit (0x4B0[0]) to renegotiate
continued...