Intel Arria 10 User Manual page 458

Refer to Arria 10 Register Map for details on the specific registers that set the
CTLE gain values/DFE taps.
b. For dynamically changing DFE and CTLE Adaptation modes, refer to CTLE
Settings in Triggered Adaptation Mode, Arria 10 Register Map and Arria 10
DFE Adaptation Tool for the list of adaptation registers. Use the
reconfiguration interface to change the register settings.
Note: You must set VGA manually for all combinations of CTLE mode and DFE
Related Information
• CTLE Settings in Triggered Adaptation Mode
• Arria 10 Register Map
Arria 10 DFE Adaptation Tool is a separate tab in the Arria 10 Register Map.
5.1.2.2. Clock Data Recovery (CDR) Unit
The PMA of each channel includes a channel PLL that you can configure as a receiver
clock data recovery (CDR) for the receiver. You can also configure the channel PLL of
channels 1 and 4 as a clock multiplier unit (CMU) PLL for the transmitter in the same
bank.
Figure 231. Channel PLL Configured as CDR
rx_serial_data
Note:
1. The Quartus® Prime Pro Edition software automatically chooses the optimal values.
5.1.2.2.1. Lock-to-Reference Mode
In LTR mode, the phase frequency detector (PFD) in the CDR tracks the receiver input
reference clock. The PFD controls the charge pump that tunes the VCO in the CDR.
The
rx_is_lockedtoref
CDR has locked to the phase and frequency of the receiver input reference clock.
Note: The phase detector (PD) is inactive in LTR mode.
® ®
Intel Arria 10 Transceiver PHY User Guide
458
modes.
Channel PLL
LTR/LTD
Controller
Phase
Detector
(PD)
N
Phase
refclk
Divider
Frequency
(1)
Detector
(PFD)
status signal is asserted active high to indicate that the
5. Arria 10 Transceiver PHY Architecture
Down
Up
Voltage
Charge Pump
Controlled
&
Oscillator
Loop Filter
Up
Down
Divider
UG-01143 | 2018.06.15
rx_is_lockedtodata
Recovered Clock
/2
L
Divider Serial Clock
(1)
(VCO)
Lock
rx_is_lockedtoref
Detect
M
(1)