Intel Arria 10 User Manual page 337

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Document
Version
Made the following changes to the Simulating the Transceiver Native PHY IP section:
• Added a footnote to inform that the "NativeLink" mode is not supported by the "Quartus Prime Pro"
edition.
• Added the "Scripting IP Simulation" flow..
• Replaced the "Generation Version Agnostic IP" and "Platform DesignerPlatform Designer Simulation
Scripts", "Use the ip-make-simscript Utility", and "How to Generate Scripts" sections with the
"Scripting IP Simulation" section.
Made the following changes to the PCI Express section:
• Updated the "How to Place Channels for PIPE Configuration" section.
• Updated the"x4 Configuration with Master Channel Adjacent to a HIP", "x4 Configuration with
Master Channel not Adjacent to a HIP", "Rate Switch Change" figures.
Made the following changes to the Other Protocols section:
• Replaced the "Design Considerations for Data Rates above 17.4 Gbps Using Arria 10 GT Channels"
section.
• Changed the title from "Design Considerations for Data Rates above 17.4 Gbps Using Arria 10 GT
Channels" to "Design Considerations for implementing Arria 10 GT Channels".
• Changed the data rate from a range of "17.4 Gbps to 28.3 Gbps" to 25.78125 Gbps.
• Changed the titles of "Valid Permutations for GT and GX Channel Configuration in Transceiver Bank
GXBL1G for Channels 0, 1, and 2" and "Valid Permutations for GT and GX Channel Configuration in
Transceiver Banks GXBL1E and GXBL1H for Channels 3, 4, and 5".
• Removed the "Native PHY IP Parameter Settings for PCS Direct Transceiver Configuration Rules"
section.
• Changed "How to Implement Designs for Data Rates Above 17.4 Gbps Using Enhanced PCS in Low
Latency Mode" section.
• Changed the "ATX PLL IP with GT Clock Lines Enabled" figure.
• Updated the "Valid Permutations for GT and GX Channel Configuration in Transceiver Bank GXBL1G
for Channels 0, 1, and 2" and "Valid Permutations for GT and GX Channel Configuration in
Transceiver Banks GXBL1E, and GXBL1H for Channels 3, 4, and 5"" tables.
Made the following changes to the CPRI section:
• Updated the "Transceiver Channel Datapath and Clocking for CPRI" figure.
• Added a note in the "Channel Width Options for Supported Serial Data Rates" table.
• Changed the fPLL supported data rate in the "TX PLL Supported Data Rates" table.
• Changed the "General and Datapath Options" table in the "Native PHY IP Parameter Settings for
CPRI" section.
Made the following changes to the Arria 10 Transceiver Protocols and PHY IP Support section:
• Moved the 19th footnote from "Protocol Preset" column to "Transceiver PHY IP Core" column.
• Changed the footnote 14 to the following: "Link training, auto speed negotiation and sequencer
functions are not included in the Native PHY IP. The user would have to create soft logic to
implement these functions when using Native PHY IP".
2016.02.11 Made the following changes to the Other Protocols section:
• Removed the "Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT Channels"
section.
• Updated the maximum data rate for GT channels to 25.8 Gbps.
2015.12.18 Made the following changes to the 1G/2.5G/10G Multi-rate Ethernet PHY IP Core section:
• Removed signals from the "XGMII Signals" table.
• Removed signals from the "PHY Interface Signals" figure.
• Changed the ordering code in the "PHY Release Information" table.
Made the following changes to the XAUI PHY IP Core section:
• Added a description to the "Implementation of the XGMII Specification in Arria 10 Devices
Configuration" figure.
Made the following changes to the 10GBASE-KR PHY IP with FEC Option section:
• Added a note to the "Parameterizing the 10GBASE-KR PHY" section.
• Added new signals to the "Control and Status Signals" table.
Changes
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Intel Arria 10 Transceiver PHY User Guide
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