Intel Arria 10 User Manual page 367

3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Port
pcie_sw_done[1:0]
atx_to_fpll_cascade_clk
fpll_to_fpll_cascade_clk
active_clk
outclk0
outclk1
outclk2
outclk3
ext_lock_detect_clklow
ext_lock_detect_fref
phase_reset
phase_en
updn
cntsel[3:0]
Related Information
• Calibration
• Reconfiguration Interface and Dynamic Reconfiguration
(57)
The fPLL and
fref
detection logic.
Direction
output
input
output
output
output
output
output
output
(57)
output
(57)
output
input
input
input
input
on page 29
signals should only be used with the Intel external soft lock
clklow
Clock Domain
Asynchronous 2-bit rate switch status output used
for PCIe protocol implementation.
N/A Enables fPLL to ATX PLL cascading
clock input port.
N/A fPLL to fPLL cascade output port
(only in Core mode)
N/A Creates an output signal that
indicates the input clock being used
by the PLL. A logic Low on this signal
indicates
a logic High indicates
being used (only in Core mode with
Clock Switchover enabled)
N/A Core output clock 0. (only in Core
mode)
There are four core fPLL output clock
output ports. The number of output
clock available depends on the
Selected reference clock source
N/A Core output clock 1. (only in Core
mode)
N/A Core output clock 2. (only in Core
mode)
N/A Core output clock 3. (only in Core
mode)
N/A Clklow output for external lock
detection. It can be exposed by
selecting the Enable clklow and
fref port.
N/A Fref output for external lock
detection It can be exposed by
selecting the Enable clklow and
fref port.
N/A Dynamic phase shift reset input
signal. To be connected to DPS soft
IP phase_reset output.
N/A Dynamic phase shift enable input
signal. To be connected to DPS soft
IP phase_en output.
N/A Dynamic phase shift updn input
signal. To be connected to DPS soft
IP updn output.
N/A Dynamic phase shift counter bus. To
be connected to DPS soft IP cntsel
output bus.
on page 502
® ®
Intel Arria
Description
is being used and
refclk0
is
refclk1
10 Transceiver PHY User Guide
367