Intel Arria 10 User Manual page 209

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
2.6.5.4.1. Clock and Reset Signals
Table 158. Clock and Reset Signals
Signal Name
Clock signals
tx_clkout
rx_clkout
csr_clk
xgmii_tx_coreclkin
xgmii_rx_coreclkin
latency_measure_clk
tx_serial_clk
rx_cdr_refclk
rx_cdr_refclk_1
rx_pma_clkout
Reset signals
reset
tx_analogreset
Direction Width
Output 1
Output 1
Input 1
Input 1
Input 1
Input 1
Input 1-3
Input 1
Input 1
Output 1
Input 1
Input 1
Description
GMII TX clock, derived from
. Provides 156.25 MHz
tx_serial_clk[1:0]
timing reference for 2.5GbE; 62.5 MHz for 1GbE.
GMII RX clock, derived from
. Provides 156.25 MHz
tx_serial_clk[1:0]
timing reference for 2.5GbE; 62.5 MHz for 1GbE.
Clock for the Avalon-MM control and status
interface. Intel recommends 125 – 156.25 MHz for
this clock.
XGMII TX clock. Provides 156.25 MHz timing
reference for 10GbE and 312.5 MHz for 1G/
2.5G/5G/10G (USXGMII) mode. Synchronous to
with zero ppm.
tx_serial_clk
XGMII RX clock. Provides 156.25 MHz timing
reference for 10GbE and 312.5 MHz for 1G/
2.5G/5G/10G (USXGMII) mode.
Sampling clock for measuring the latency of the
16-bit GMII datapath. This clock operates at 80
MHz and is available only when the IEEE 1588v2
feature is enabled.
Serial clock from transceiver PLLs.
• 2.5GbE: Connect bit [0] to the transceiver PLL.
This clock operates at 1562.5 MHz.
• 1GbE: Connect bit [1] to the transceiver PLL.
This clock operates at 625 MHz.
• 10GbE: Connect bit [2] to the transceiver PLL.
This clock operates at 5156.25 MHz.
• 1G/2.5G/5G/10G (USXGMII) mode: Connect bit
[0] to 5156.25 MHz.
125-MHz RX CDR reference clock for 1GbE and
2.5GbE
RX CDR reference clock for 10GbE. The frequency
of this clock can be either 322.265625 MHz or
644.53125 MHz, as specified by the Reference
clock frequency for 10 GbE (MHz) parameter
setting.
Recovered clock from CDR, operates at the
following frequency:
• 1GbE: 125 MHz
• 2.5GbE: 312.5 MHz
• 5GbE/10GbE: 322.265625 MHz
Active-high global reset. Assert this signal to
trigger an asynchronous global reset.
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the analog block on the TX
path.
® ®
Intel Arria 10 Transceiver PHY User Guide
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