Intel Arria 10 User Manual page 161

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Addr Bit
0x482 1
2
3
4
7
2.6.3.6.4. PMA Registers
The PMA registers allow you to reset the PMA, customize the TX and RX serial data
interface, and provide status information.
Table 125. 1G Data Mode
Addr Bit
0x4A8 0 RW
1 RW
2 RW
3 RW
4 RW
0x4A9 0 R
1 R
2 R
3 R
4 R
5 R
6 R
Table 126. PMA Registers
Address Bit
0x444 1
2
3
0x461 0
Access Name
RO
HI_BER
RO
BLOCK_LOCK
RO
TX_FIFO_FULL
RO
RX_FIFO_FULL
RO
Rx_DATA_READY
R/W Name
tx_invpolarity
rx_invpolarity
rx_bitreversal_enable
rx_bytereversal_enable
force_electrical_idle
rx_syncstatus
rx_patterndetect
rx_rlv
rx_rmfifodatainserted
rx_rmfifodatadeleted
rx_disperr
rx_errdetect
R/W Name
RW
reset_tx_digital
RW
reset_rx_analog
RW
reset_rx_digital
RW
phy_serial_loopback
Description
High BER status. When set to 1, the PCS reports a high
BER. When set to 0, the PCS does not report a high
BER.
Block lock status. When set to 1, the PCS is locked to
received blocks. When set to 0, the PCS is not locked to
received blocks.
When set to 1, the
TX_FIFO
When set to 1, the
RX_FIFO
When set to 1, indicates the PHY is ready to receive
data.
Description
When set, the TX interface inverts the polarity of
the TX data to the 8B/10B encoder.
When set, the RX channels inverts the polarity of
the received data to the 8B/10B decoder.
When set, enables bit reversal on the RX interface
to the word aligner.
When set, enables byte reversal on the RX interface
to the byte deserializer.
When set, forces the TX outputs to electrical idle.
When set, the word aligner is synchronized.
GbE word aligner detected comma.
Run length violation.
Rate match FIFO inserted code group.
Rate match FIFO deleted code group.
RX 8B10B disparity error.
RX 8B10B error detected.
Description
Writing a 1 asserts the internal TX digital reset signal. You
must write a 0 to clear the reset condition.
Writing a 1 causes the internal RX analog reset signal to be
asserted. You must write a 0 to clear the reset condition.
Writing a 1 causes the internal RX digital reset signal to be
asserted. You must write a 0 to clear the reset condition.
Writing a 1 puts the channel in serial loopback mode.
® ®
Intel Arria
is full.
is full.
continued...
10 Transceiver PHY User Guide
161