Intel Arria 10 User Manual page 180

Signal Name
tx_latency_adj_10
g[15:0]
rx_latency_adj_1
g[21:0]
tx_latency_adj_1
g[21:0]
2.6.4.6.7. MII
Table 142. MII Signals
Name
MII Transmit Interface
mii_tx_d[3:0]
mii_tx_en
mii_tx_err
MII Receive Interface
mii_rx_d[3:0]
mii_rx_dv
mii_rx_err
mii_col
mii_crs
2.6.4.6.8. Dynamic Reconfiguration Interface
You can use the dynamic reconfiguration interface signals to dynamically change
between 1G and 10G data rates.
Table 143. Dynamic Reconfiguration Interface Signals
Signal Name
Output
rc_busy
® ®
Intel Arria 10 Transceiver PHY User Guide
180
Direction Clock Domain
Output Synchronous to
xgmii_tx_clk
Output Synchronous to
gmii_rx_clk
Output Synchronous to
gmii_tx_clk
Directi
on
Input MII transmit data bus.
Input
Assert this signal to indicate that the data on
Input Assert this signal to indicate to the PHY device that the frame sent is invalid.
Output MII receive data bus.
Output
Asserted to indicate that the data on
asserted during frame reception, from the first preamble byte until the last byte of
the CRC field is received.
Output Asserted by the PHY to indicate that the current frame contains errors.
Output Collision detection. Asserted by the PCS function to indicate that a collision was
detected during frame transmission.
Output Carrier sense detection. Asserted by the PCS function to indicate that a transmit or
receive activity is detected on the Ethernet line.
Direction Clock Domain
Synchronous to
mgmt_clk
2. Implementing Protocols in Arria 10 Transceivers
Description
When you enable 1588, this signal outputs the real time
latency in XGMII clock cycles (156.25 MHz) for the TX
PCS and PMA datapath for 10G mode. Bits 0 to 9
represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
When you enable 1588, this signal outputs the real time
latency in GMII clock cycles (125 MHz) for the RX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the
fractional number of clock cycles. Bits 10 to 21 represent
the number of clock cycles.
When you enable 1588, this signal outputs the real time
latency in GMII clock cycles (125 MHz) for the TX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the
fractional number of clock cycles. Bits 10 to 21 represent
the number of clock cycles.
Description
mii_tx_d[3:0]
mii_rx_d[3:0]
Description
When asserted, indicates that reconfiguration is in
progress. Synchronous to the
only exposed under the following condition:
UG-01143 | 2018.06.15
is valid.
is valid. The signal stays
. This signal is
mgmt_clk
continued...