Intel Arria 10 User Manual page 125

Transceiver phy
Hide thumbs Also See for Arria 10:
Table of Contents

Advertisement

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
The following 10GBASE-R variants area available from presets:
10GBASE-R
10GBASE-R Low Latency
10GBASE-R Register Mode
10GBASE-R w/ KR-FEC
Intel recommends that you use the presets for selecting the suitable 10GBASE-R
variants directly if you are configuring through the Native PHY IP core.
Figure 55.
Transceiver Channel Datapath and Clocking for 10GBASE-R
10.3125 Gbps
Notes:
1. Value based on the clock division factor chosen.
2. Value calculated as data rate / PCS-PMA interface width.
3. This block is in Phase Compensation mode for the 10GBASE-R configuration and register mode for the 10GBASE-R with 1588 configuration.
4. This block is in 10GBASE-R mode for the 10GBASE-R configuration and register mode for the 10GBASE-R with 1588 configuration.
10GBASE-R with IEEE 1588v2
When choosing the 10GBASE-R PHY with IEEE 1588v2 mode preset, the hard TX and
RX FIFO are set to register mode. The output clock frequency of
rx_clkout
if the PCS-PMA interface is 40-bit,
Gbps/40-bit = 257.8125 MHz.
The 10GBASE-R PHY with IEEE 1588v2 creates the soft TX phase compensation FIFO
and the RX clock compensation FIFO in the FPGA core so that the effective XGMII data
is running at 156.25 MHz interfacing with the MAC layer.
Transmitter PMA
Transmitter Enhanced PCS
40
PRBS
Generator
Parallel Clock
@ 257.8125 MHz (2)
Receiver Enhanced PCS
Receiver PMA
40
66
PRBS
Verifier
Clock Generation Block (CGB)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
to the FPGA fabric is based on the PCS-PMA interface width. For example,
64
66
PRP
Generator
64
PRP
Verifier
Parallel Clock
@ 257.8125 MHz (2)
10GBASE-R
BER Checker
Clock Divider
Parallel and Serial Clocks
and
tx_clkout
rx_clkout
®
Intel
FPGA
Fabric
TX
Data &
Control
64 + 8
@ 156.25 MHz
from XGMII
tx_clkout
tx_pma_div_clkout
rx_pma_div_clkout
RX
Data &
Control
64 + 8
@ 156.25 MHz
from XGMII
rx_clkout
ATX PLL
fPLL
CMU PLL
Serial Clock
Input Reference Clock
and
tx_clkout
run at 10.3125
®
Arria
10 Transceiver PHY User Guide
125

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents