Intel Arria 10 User Manual page 205

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Addr
0x06
an_expansion
0x07
device_next_page
0x08
partner_next_pag
e
0x09:0x0F Reserved
0x10
scratch
0x11
rev
0x12:0x13
link_timer
0x14:0x1F Reserved
0x400
usxgmii_control
Name
•
Bits [8:7]:
— 00: No PAUSE.
— 01: Symmetric PAUSE.
— 10: Asymmetric PAUSE towards the link partner.
— 11: Asymmetric and symmetric PAUSE towards
the link device.
•
Bit [6]:
HD
is supported.
•
Bit [5]:
FD
is supported.
• The rest of the bits are reserved.
The PCS capabilities and auto-negotiation status.
Bit [1]:
PAGE_RECEIVE
the partner_ability register has been updated. This bit is
automatically cleared once it is read.
Bit [0]:
LINK_PARTNER_AUTO_NEGOTIATION_ABLE
value of "1" indicates that the link partner supports
auto-negotiation.
The PHY does not support the next page feature. These
registers are always set to 0.
—
Provides a memory location to test read and write
operations.
The current version of the PHY IP core.
21-bit auto-negotiation link timer.
• Offset 0x12: link_timer[15:0]. Bits [8:0] are always
be set to 0.
• Offset 0x13: link_timer[20:16] occupies the lower 5
bits. The remaining 11 bits are reserved and must
always be set to 0.
—
Control Register
Bit [0]:
USXGMII_ENA
• 0: 10GBASE-R mode
• 1: USXGMII mode
Bit [1]:
USXGMII_AN_ENA
is set to 1:
• 0: Disables USXGMII Auto-Negotiation and manually
configures the operating speed with the
USXGMII_SPEED
• 1: Enables USXGMII Auto-Negotiation, and
automatically configures operating speed with link
partner ability advertised during USXGMII Auto-
Negotiation.
Description
. The PAUSE support.
PS
. A value of "1" indicates that half-duplex
. A value of "1" indicates that full-duplex
. A value of "1" indicates that
:
is used when
USXGMII_ENA
register.
®
Intel
Access HW Reset
Value
RO
RO
RO
—
—
RO
RO
. A
RO
RO
—
RW
RO Current
version of
the PHY
RW
—
—
RW 0x0
RW 0x1
continued...
®
Arria 10 Transceiver PHY User Guide
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0
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0
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