Intel Arria 10 User Manual page 489

5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
PCS-PMA Supported Word
Interface Aligner Modes
Width
16 Bit slip
Manual
20 Bit slip
Manual
Deterministic latency
(CPRI mode only)
Supported
rx_std_wa_patte
Word Aligner
behavior
rnalign
Pattern
Lengths
16
rx_std_wa_patt
has no
ernalign
effect on word
alignment. The
double width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
8, 16, 32 Word alignment is
controlled by
rising-edge of
rx_std_wa_patt
.
ernalign
7
rx_std_wa_patt
has no
ernalign
effect on word
alignment. The
double width word
aligner updates the
word boundary,
only when the
FPGA fabric-
asserted BITSLIP
signal toggles.
7, 10, 20, 40 Word alignment is
controlled by rising
edge of
rx_std_wa_patt
.
ernalign
10 Word alignment is
controlled by
rx_std_wa_patt
(edge-
ernalign
sensitive to this
signal) and the
deterministic
latency state
machine which
controls the PMA to
rx_syncstatus rx_patterndetect
behavior behavior
appears in the
current word
boundary.
N/A N/A
Stays high after Asserted high for
the word aligner one parallel clock
aligns to the word cycle when the word
alignment pattern. alignment pattern
Goes low on appears in the
receiving a rising current word
edge on boundary.
rx_std_wa_patt
until a
ernalign
new word
alignment pattern
is received.
N/A N/A
Stays high after Asserted high for
the word aligner one parallel clock
aligns to the word cycle when the word
alignment pattern. alignment pattern
Goes low on appears in the
receiving a rising current word
edge on boundary.
rx_std_wa_patt
until a
ernalign
new word
alignment pattern
is received.
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continued...
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Intel Arria 10 Transceiver PHY User Guide
489