Samsung S5PC100 User Manual page 1043

S5PC100 USER'S MANUAL (REV1.0)
3.6 VTIME CONTROLLER OPERATION
VTIME has two blocks. One is VTIME_RGB_TV for RGB interface and ITU-R601/ 656 interface timing control.
The other is VTIME_I80 for indirect i80 interface timing control.
3.6.1 RGB Interface Controller
The VTIME generates the control signals such as, RGB_VSYNC, RGB_HSYNC, RGB_VDEN and RGB_VCLK
signal for RGB interface. These control signals are highly related with the configuration on the VIDTCON0/1/2
registers in the VSFR register. Based on these programmable configurations of the display control registers in
VSFR, the VTIME module generates the programmable control signals suitable for the support of many different
types of display device.
The RGB_VSYNC signal asserts to cause the LCD's line pointer to start over at the top of the display. The
configuration of both HOZVAL field and LINEVAL registers controls pulse generation of RGB_VSYNC and
RGB_HSYNC. The size of the LCD panel according to the following equations determines HOZVAL and
LINEVAL:
HOZVAL = (Horizontal display size) -1
LINEVAL = (Vertical display size) –1
The CLKVAL field in the VIDCON0 register controls rate of RGB_VCLK signa. The table below defines the
relationship of RGB_VCLK and CLKVAL. The minimum value of CLKVAL is 1.
RGB_VCLK (Hz) =HCLK/ (CLKVAL+1) where CLKVAL >= 1
Table 9.1-5 Relation 16BPP between VCLK and CLKVAL (TFT, Frequency of Video Clock Source=60MHz)
CLKVAL
2
3
:
63
60MHz/X
60 MHz/3
60 MHz/4
:
60 MHz/64
DISPLAY CONTROLLER
VCLK
20.0 MHz
15.0 MHz
:
937.5 kHz
9.1-29