Fec Receive Fifo Data Register (Fecrfdr); Fec Receive Fifo Status Register (Fecrfsr) - Freescale Semiconductor MCF5480 Reference Manual

Bits Name
31–4 —
3–0 X_WMRK

30.3.3.18 FEC Receive FIFO Data Register (FECRFDR)

This is the main interface port for the FIFO. Data that is to be buffered in the FIFO or that has been buffered
in the FIFO is accessed through this register. It can be accessed by byte, word, or longword. It is
recommended to align all accesses to the most significant byte (big endian) of the data port, using the
address of FECRFDR for byte, word, and longword transactions. However, accessing the data port at
FECRFDR+ 1,
+ 2, or + 3 for bytes, or FECRFDR+ 2 for words is also acceptable.
31 30 29
R
W
Reset 0 0 0
15 14 13
R
W
Reset 0 0 0
Reg
Addr
Bits Name
31–0 FIFO_DATA Receive FIFO data. Reading this register will extract received data from the FIFO.

30.3.3.19 FEC Receive FIFO Status Register (FECRFSR)

The FIFO receive status register contains bits that provide information about the status of the FIFO
controller. Some of the bits of this register are used to generate DMA requests.
30-26
Table 30-24. FECTFWR Field Descriptions
Reserved, should be cleared.
Transmit FIFO watermark. Frame transmission will begin when the number of bytes selected by this
field have been written into the transmit FIFO or if an end of frame has been written to the FIFO or
if the FIFO is full before the selected number of bytes have been written.
Number of bytes written = 64 (X_WMRK + 1)
28 27 26 25
0 0 0 0
12 11 10 9
0 0 0 0
MBAR + 0x9184 (FEC0), 0x9984 (FEC1)
Figure 30-21. FEC Receive FIFO Data Register (FECRFDR)
Table 30-25. FECRFDR Field Descriptions
MCF548x Reference Manual, Rev. 3
Descriptions
24 23 22 21
FIFO_DATA
0 0 0 0
8 7 6 5
FIFO_DATA
0 0 0 0
Descriptions
20 19 18 17
0 0 0 0
4 3 2 1
0 0 0 0
Freescale Semiconductor
16
0
0
0