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DMA Serial Peripheral Interface (DSPI)
Field
23–16
Peripheral chip select n. Selects which DSPI_PCSn signals are asserted for the transfer. This bit is used only in SPI
PCSn
master mode.
0 Negate the DSPI_PCSn signal
1 Assert the DSPI_PCSn signal
Note: DSPI_PCS7, DSPI_PCS6, DSPI_PCS5, DSPI_PCS4 and DSPI_PCS1 are not implemented on this device.
Therefore, these corresponding bits are reserved.
15–0
Transmit data. Holds SPI data to be transferred according to the associated SPI command.
TXDATA
Note: TXDATA is used in slave mode.
29.3.7
DSPI POP RX FIFO Register (DSPI_POPR)
The DSPI_POPR provides a means to read the RX FIFO. See
Mechanism" for a description of the RX FIFO operations. Eight or 16-bit read accesses to the DSPI_POPR
read from the RX FIFO and update the counter and pointer.
Address: 0xFC05_C038 (DSPI_POPR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R 0
0
0
0
0
W
Reset 0
0
0
0
0
Field
31–16
Reserved, must be cleared.
15–0
Received data. Contains the SPI data from the RX FIFO entry pointed to by the pop next data pointer
RXDATA
(DSPI_SR[POPNXTPTR]).
29.3.8
DSPI Transmit FIFO Registers 0–15 (DSPI_TXFRn)
The DSPI_TXFRn registers provide visibility into TX FIFO for debugging purposes. Each register is an
entry in TX FIFO. The registers are read-only and cannot be modified. Reading the DSPI_TXFRn registers
does not alter the state of TX FIFO. The 16-entry deep FIFO is implemented with 16 registers,
DSPI_TXFR0–15.
29-18
Table 29-8. DSPI_PUSHR Field Descriptions (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 29-8. DSPI_POPR Register
Table 29-9. DSPI_POPR Field Descriptions
MCF52277 Reference Manual, Rev. 1
Description
Section 29.4.2.5, "RX FIFO Buffering
0
0
0
0
0
0
0
0
0
0
0
Description
Access: User read-only
9
8
7
6
5
4
3
RXDATA
0
0
0
0
0
0
0
0
Freescale Semiconductor
2
1
0
0
0
0
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