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Analog-to-Digital Converter (ADC)
3.7.2 ADC Data Register High
In left justified mode, this 8-bit result register holds the eight MSBs of the 10-bit result. This register is
updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of
ADRL until ADRL is read. Until ADRL is read, all subsequent ADC results will be lost.
Address:
Read:
Write:
Reset:
Figure 3-5. ADC Data Register High (ADRH) Left Justified Mode
In right justified mode, this 8-bit result register holds the two MSBs of the 10-bit result. All other bits read
as 0. This register is updated each time a single channel ADC conversion completes. Reading ADRH
latches the contents of ADRL until ADRL is read. Until ADRL is read, all subsequent ADC results will be
lost.
Address:
Read:
Write:
Reset:
Figure 3-6. ADC Data Register High (ADRH) Right Justified Mode
3.7.3 ADC Data Register Low
In left justified mode, this 8-bit result register holds the two LSBs of the 10-bit result. All other bits read as
0. This register is updated each time a single channel ADC conversion completes. Reading ADRH latches
the contents of ADRL until ADRL is read. Until ADRL is read, all subsequent ADC results will be lost.
Address:
Read:
Write:
Reset:
Figure 3-7. ADC Data Register Low (ADRL) Left Justified Mode
In right justified mode, this 8-bit result register holds the eight LSBs of the 10-bit result. This register is
updated each time an ADC conversion completes. Reading ADRH latches the contents of ADRL until
ADRL is read. Until ADRL is read, all subsequent ADC results will be lost.
54
$0041
Bit 7
6
5
AD9
AD8
AD7
R
R
R
R
= Reserved
$0041
Bit 7
6
5
0
0
0
R
R
R
R
= Reserved
$0042
Bit 7
6
5
AD1
AD0
0
R
R
R
R
= Reserved
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
4
3
2
AD6
AD5
AD4
R
R
R
Unaffected by reset
4
3
2
0
0
0
R
R
R
Unaffected by reset
4
3
2
0
0
0
R
R
R
Unaffected by reset
1
Bit 0
AD3
AD2
R
R
1
Bit 0
AD9
AD8
R
R
1
Bit 0
0
0
R
R
Freescale Semiconductor
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