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System Control Module (SCM)
Field
31–10
Reserved, must be cleared.
9
Global burst enable for reads. Allows bursts to happen on read transactions from the crossbar switch slaves to the
GBR
USB On-the-Go module.
0 Read bursts are disabled.
1 Read bursts are enabled.
Note: If GBR and GBW are cleared, then SBE is ignored.
8
Global burst enable for writes. Allows bursts to happen on write transactions to the crossbar switch slaves from the
GBW
USB On-the-Go module.
0 Write bursts are disabled.
1 Write bursts are enabled.
Note: If GBR and GBW are cleared, then SBE is ignored.
7–0
Slave burst enable. Allows bursts to happen to/from the crossbar switch slaves. The only valid settings for this field
SBE
are 0x00 or 0xFF.
0x00 Bursts disabled.
0xFF Bursts enabled. The GBR and GBW bits determine the burst direction. If neither is set, then this bit has no
effect.
Else Reserved.
12.2.7
Core Fault Address Register (CFADR)
The CFADR captures the address of the last core data access terminated with an error response. It should
be noted that if the faulting data transfer is a burst write, the captured fault address is valid only to the burst
transfer size. For example, if the data transfer was a 16-byte burst, the captured fault address is only valid
to the modulo-16 address. The low-order four bits are undefined. This behavior is the result of the data
pipelining typically required to support burst writes in slave devices. This register can only be read; any
attempted write is ignored.
Address: 0xFC04_0070 (CFADR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
Indicates the faulting address of the last core access terminated with an error response.
ADDR
12.2.8
Core Fault Interrupt Enable Register (CFIER)
The CFIER register enables the system bus-error interrupt. See
Modules,"
for more information of the interrupt controller.
12-10
Table 12-8. BCR Field Descriptions
Figure 12-16. Core Fault Address Register (CFADR)
Table 12-9. CFADR Field Descriptions
MCF52277 Reference Manual, Rev. 1
Description
ADDR
Description
Chapter 15, "Interrupt Controller
Access: User read-only
8
7
6
5
4
3
2
1
0
Freescale Semiconductor
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