Base Address Register Overview - Freescale Semiconductor MCF5480 Reference Manual

MCF548x Space
0
Register Space
MBAR
1G
Window 0
XLB
Initiator
Windows
Window 1
2G
Window 2
3G
4G
Associated with PCI
Prefetchable Memory
Associated with PCI I/O
Associated with PCI
Non-Prefetchable Memory
19.5.2.1.3

Base Address Register Overview

Table 19-58 shows the available accessibility for all PCI associated base address and translation address
registers in the MCF548x.
Base Address
Register
BAR0
BAR1
TBATR0
19-74
Window 0
Translation
Not Recommended
Window 1
Translation
Not Recommended
Window 2
Translation
Window 0 Base Address = 0x40
Window 0 Address Mask = 0x1F
Window 0 Translation Address = 0x00
Window 1 Base Address = 0x70
Window 1 Address Mask = 0x0F
Window 1 Translation Address = 0x70
Figure 19-55. Outbound Address Map
Table 19-58. Address Register Accessibility
Register Function
PCI Base Address Register 0
(256 Kbyte)
PCI Base Address Register 1
(1 Gbyte)
Target Base Address Translation
Register 0 (256 Kbyte)
MCF548x Reference Manual, Rev. 3
PCI Space
(Memory View)
0 0
Window 0
1G 1G
MCF548X
Memory
2G 2G
MCF548X
Memory
3G 3G
Window 2
4G 4G
Window 2 Base Address = 0x80
Window 2 Address Mask = 0x3F
Window 2 Translation Address = 0xC0
PCI Bus
Configuration
Access
X
X
PCI Space (Configuration
(I/O View) View)
0
1G
Window 1
2G
3G
4G
Processor Any XL Bus
Access Master Access
X X
X X
X X
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