Event Counter Value Register (Ecnt_Val) - Freescale Semiconductor SC140 DSP Core Reference Manual

Event Counter Registers
Name Description
ECNTEN Event Counter Enable — Used to
Bits 7–4 enable the ECNT operation. When
ECNTEN is set to 1111, ECNT is
operational and will count events
according to ECNTWHAT bits, which
select the source for that count. If bits
ECNTEN are set to enable the operation
of the event counter when an event is
detected or signal EE2 is asserted, the
EOnCE overwrites these bits to 1111
one cycle after the appearance of the
event.
When the event counter is programmed
to be enabled by the same event that it
has to count, the first such event enables
the event counter and is counted as the
first event.
When the event counter is enabled by a
given event, but is programmed to count
a different event, the counter does not
include the enabling event in the count.
ECNTWHAT Events to be Counted — Determines
Bits 3–0 what is to be counted by ECNT.

4.8.2 Event Counter Value Register (ECNT_VAL)

This 32-bit register is used to determine how many events the event counter should count before it
generates the count event signal. ECNT_VAL is a down-counter. The MSB is always zero, so the range is
from $7FFF FFFF to $0000 0000. When the register is written, the MSB should be written to zero for
software compatibility.
4-52
Table 4-18. ECNT_CTRL Description (Continued)
Settings
0000 =.The event is disabled.
0001 =.The event counter is disabled, but is enabled
when an event is detected by the EDCA0.
0010 =.The event counter is disabled, but is enabled
when an event is detected by the EDCA1.
0011 =.The event counter is disabled, but is enabled
when an event is detected by the EDCA2.
0100 =.The event counter is disabled, but is enabled
when an event is detected by the EDCA3.
0101 =.The event counter is disabled, but is enabled
when an event is detected by the EDCA4.
0110 =.The event counter is disabled, but is enabled
when an event is detected by the EDCA5.
0111 =.The event counter is disabled, but is enabled
when an event is detected by the optional external
EDCA6.
1000 =.The event counter is disabled, but is enabled
when an event is detected by the optional external
EDCA7.
1001 =.The event counter is disabled, but is enabled
when an event is detected by EDCD.
1010 =.The event counter is disabled, but is enabled
when signal EE2 is asserted and EE2 is
programmed in the EE_CTRL register as an input.
1011 =.Reserved
1100 =.Reserved
1101 =.Reserved
1110 =.Reserved
1111 =.The event counter is enabled.
0000 =.Count event0 occurrence.
0001 =.Count event1 occurrence.
0010 =.Count event2 occurrence.
0011 =.Count event3 occurrence.
0100 =.Count event4 occurrence.
0101 =.Count event5 occurrence.
0110 =.Count optional external event6 occurrence
0111 =.Count optional external event7 occurrence
1000 =.Count eventD occurrence.
1001 =.Count executions of DEBUGEV instruction.
1010 =.Count trace events (data moved to the buffer).
1011 =.Count executed execution sets.
1100 =.Count core clocks.
1101 =.Count off-core event 0
1110 =.Count off-core event 1
1111 = Reserved
SC140 DSP Core Reference Manual