Mmu Data Access Protection Register - Freescale Semiconductor PowerPC MPC823 Reference Manual

Memory Management Unit
11.6.1.9 MMU DATA ACCESS PROTECTION REGISTER. The MMU data access
protection (MD_AP) register contains the access protection group for the data memory
management unit.
MD_AP
BIT 0 1 2
FIELD GP0
RESET —
R/W R/W
ADDR
BIT 16 17 18
FIELD GP8
RESET —
R/W R/W
ADDR
NOTE: — = Undefined.
GPx—Group Protection
In domain manager mode, these bits have the following settings.
00 = No access.
01 = Client-access permission defined by page protection bits.
10 = Reserved.
11 = Manager-free access.
In PowerPC mode, the GPx bits have these settings and are privilege and problem state
(Ks and Kp) in the PowerPC Microprocessor Family: The Programming Environment for
32-Bit Microprocessors manual:
00 = All accesses are considered privileged.
01 = Access permission defined by page protection bits.
10 = Problem and privileged interpretation is swapped.
11 = All accesses are considered problem.
Freescale Semiconductor, Inc.
3 4 5 6
GP1 GP2 GP3
— — —
R/W R/W R/W
19 20 21 22
GP9 GP10 GP11
— — —
R/W R/W R/W
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7 8 9 10 11
GP4 GP5
— —
R/W R/W
SPR 794
23 24 25 26 27
GP12 GP13
— —
R/W R/W
SPR 794
12 13 14 15
GP6 GP7
— —
R/W R/W
28 29 30 31
GP14 GP15
— —
R/W R/W
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