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Address: 0xFC04_0077 (CFATR)
7
R
WRITE
W
Reset:
–
Field
7
Indicates the direction of the last faulted core access.
WRITE
0 Core read access.
1 Core write access.
6–4
Indicates the size of the last faulted core access.
SIZE
000 8-bit core access.
001 16-bit core access.
010 32-bit core access.
Else Reserved.
3
Indicates if last faulted core access was cacheable.
CACHE
0 Non-cacheable
1 Cacheable
2
Reserved, should be cleared.
1
Indicates the mode the device was in during the last faulted core access.
MODE
0 User mode
1 Supervisor mode
0
Defines the type of last faulted core access.
TYPE
0 Instruction
1 Data
11.2.13 Core Fault Data Register (CFDTR)
The CFDTR is a read-only register for capturing the data associated with the last faulted processor write
data access from the device's internal bus. The CFDTR is only valid for faulted internal bus write accesses,
CFLOC[LOC] = 0.
Address: 0xFC04_007C (CFDTR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Freescale Semiconductor
6
5
SIZE
–
–
Figure 11-21. Core Fault Attributes Register (CFATR)
Table 11-13. CFATR Field Descriptions
Figure 11-22. Core Fault Data Register (CFDTR)
MCF5329 Reference Manual, Rev 3
4
3
2
CACHE
0
–
–
–
Description
CFDTR
System Control Module (SCM)
Access: User read-only
1
0
MODE
TYPE
–
–
Access: User read-only
8
7
6
5
4
3
2
1
0
11-13
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