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System Control Module (SCM)
Address: 0xFC04_0077 (CFATR)
7
R
WRITE
W
Reset:
–
Field
7
Indicates the direction of the last faulted core access.
WRITE
0 Core read access.
1 Core write access.
6–4
Indicates the size of the last faulted core access.
SIZE
000 8-bit core access.
001 16-bit core access.
010 32-bit core access.
Else Reserved.
3–2
Reserved, must be cleared.
1
Indicates the mode the device was in during the last faulted core access.
MODE
0 User mode
1 Supervisor mode
0
Defines the type of last faulted core access.
TYPE
0 Instruction
1 Data
12.2.11 Core Fault Data Register (CFDTR)
The read-only CFDTR captures the data associated with the last faulted processor write data access from
the device's internal bus. The CFDTR is valid only for faulted internal write accesses. The contents of this
register are not valid if the last fault occurred on the core's local bus (CFLOC[LOC] = 1) or if the faulting
data transfer is a burst write because the captured data value is not guaranteed to be exactly associated with
the faulting transfer. This behavior is the result of the data pipelining needed to support burst writes in slave
devices.
This register is not updated on internal read access faults. This register can only be read; any attempted
write is ignored.
Address: 0xFC04_007C (CFDTR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
12-12
6
5
SIZE
–
–
Figure 12-19. Core Fault Attributes Register (CFATR)
Table 12-12. CFATR Field Descriptions
Figure 12-20. Core Fault Data Register (CFDTR)
MCF52277 Reference Manual, Rev. 1
4
3
2
0
0
–
–
–
Description
CFDTR
Access: User read-only
1
0
MODE
TYPE
–
–
Access: User read-only
8
7
6
5
4
3
2
1
0
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