Gpio Input Enable Register (Gier) - Freescale Semiconductor MSC8144E Reference Manual

Name Reset
UTP_ENABLE
7
—
6–4
ENET_SGMII_MODE1
3
ENET_SGMII_MODE0
2
—
1–0

8.2.9 GPIO Input Enable Register (GIER)

GIER
Bit 31 30
IE31 IE30
Type
Reset 0 0
Bit 23 22
IE23 IE22
Type
Reset 0 0
Bit 15 14
IE15 IE14
Type
Reset 0 0
Bit 7 6
IE7 IE6
Type
Reset 0 0
GIER enables/disables the individual GPIO signals.
accesses can only be performed in Supervisor mode.
Name Reset
IE[31–0]
31–0
Freescale Semiconductor
Table 8-8. QECTLR Bit Descriptions (Continued)
Description
0 UTOPIA Enable
Enables the UTOPIA interface.
0 Reserved. Write to 0 for future compatibility.
0 SGMII Mode for Ethernet Controller 2
Selects SGMII mode for Ethernet controller
2.
0 SGMII Mode for Ethernet Controller 1
Selects SGMII mode for Ethernet controller
1.
0 Reserved. Write to 0 for future compatibility.
GPIO Input Enable Register
29 28
IE29 IE28
0 0
21 20
IE21 IE20
0 0
13 12
IE13 IE12
0 0
5 4
IE5 IE4
0 0
Table 8-9. GIER Bit Descriptions
Description
0 Input Enable 31–0
Each bit in this field enables/disables the
individual I/O signals corresponding to the
bit index number.
MSC8144E Reference Manual, Rev. 3
0 UTOPIA not enabled.
1 UTOPIA enabled.
0 SGMII not selected.
1 SGMII selected.
0 SGMII1 not selected.
1 SGMII1 selected.
27 26
IE27 IE26
R/W
0 0
19 18
IE19 IE18
R/W
0 0
11 10
IE11 IE10
R/W
0 0
3 2
IE3 IE2
R/W
0 0
The register is reset on a Hard reset. Write
Table 8-9 lists the GIER bit field descriptions.
0 Input is disabled.
1 Input is enabled.
Detailed Register Descriptions
Settings
Offset 0x24
25 24
IE25 IE24
0 0
17 16
IE17 IE16
0 0
9 8
IE9 IE8
0 0
1 0
IE1 IE0
0 0
Settings
8-11