Low-Power Mode Operation; Interrupt/Gpio Pin Descriptions; Memory Map/Register Definition - Freescale Semiconductor MCF5329 Reference Manual

Devices supported: mcf5327; mcf5328; mcf53281; mcf5329
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Edge Port Module (EPORT)
15.2

Low-Power Mode Operation

This section describes the operation of the EPORT module in low-power modes. For more information on
low-power modes, see
Chapter 8, "Power Management". Table 15-1
low-power modes and describes how this module may exit each mode.
The wakeup control register (WCR) in the system control module specifies
the interrupt level at or above what is needed to bring the device out of a
low-power mode.
Table 15-1. Edge Port Module Operation in Low-Power Modes
Low-power Mode
Wait
Doze
Stop
In wait and doze modes, the EPORT module continues to operate as it does in run mode. It may be
configured to exit the low-power modes by generating an interrupt request on a selected edge or a low level
on an external pin. In stop mode, no clocks are available to perform the edge-detect function. Only the
level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate
an interrupt (if enabled) to exit stop mode.
In stop mode, the input pin synchronizer is bypassed for the level-detect
logic because no clocks are available.
15.3

Interrupt/GPIO Pin Descriptions

All EPORT pins default to general-purpose input pins at reset. The pin value is synchronized to the rising
edge of FB_CLK when read from the EPORT pin data register (EPPDR). The values used in the edge/level
detect logic are also synchronized to the rising edge of FB_CLK. These pins use Schmitt-triggered input
buffers with built-in hysteresis designed to decrease the probability of generating false, edge-triggered
interrupts for slow rising and falling input signals.
When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding
bit in the EPORT data register (EPDR). All bits in the EPDR are set at reset.
15.4

Memory Map/Register Definition

This subsection describes the memory map and register structure. Refer to
the EPORT memory map.
15-2
NOTE
EPORT Operation
Normal
Any IRQn interrupt at or above level in WCR
Normal
Any IRQn interrupt at or above level in WCR
Level-sensing only
Any IRQn interrupt set for level-sensing at or
above level in WCR. See note below.
NOTE
MCF5329 Reference Manual, Rev 3
shows EPORT-module operation in
Mode Exit
Table 15-2
for a description of
Freescale Semiconductor

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