Port A Registers; Port A Open-Drain Register (Paodr); Port A Data Register (Padat) - Freescale Semiconductor MPC850 User Manual

34.2.1 Port A Registers

Port A has four memory-mapped control registers, described in the following sections.

34.2.1.1 Port A Open-Drain Register (PAODR)

The port A open-drain register (PAODR), shown in Figure 34-1, determines which port
signals with serial channel output capability are configured in a normal or wired-OR
configuration. Setting the PAODR bits configure the signals for open-drain operation.
Bit 0 1 2
Field
Reset
R/W
Addr
Figure 34-1. Port A Open-Drain Register (PAODR)
Table 34-2 describes PAODR bits.
Bits Name
0–8, 10, — Reserved, always reads as 0.
11, 13, 15
9, 12, 14 ODn Tells how the corresponding port A signal is interpreted.
0 The signal is actively driven as an output.
1 The signal is an open-drain driver. Outputs are actively driven low. Otherwise, it is three-stated.

34.2.1.2 Port A Data Register (PADAT)

Reading the port A data (PADAT) register returns the value of the signal, regardless of
whether the signal is an input or output. Comparing written data with the data on the signal
can detect output conflicts. A write to a PADAT bit is latched; if the bit is configured as an
output, the value latched for that bit is driven onto its respective signal. PADAT can be read
or written at any time, is not initialized, and is undefined at reset.
Bit 0 1
Field — —
Reset — —
R/W
Addr
3 4 5 6 7
—
Table 34-2. PAODR Bit Descriptions
2 3 4 5
— — D4 D5
— — 0 0
R/W R/W R/W R/W R/W R/W
Figure 34-2. Port A Data Register (PADAT)
Chapter 34. Parallel I/O Ports
8 9 10
OD9 —
0
R/W
0x954
Description
6 7 8 9
D6 D7 D8 D9
0 0 0 0
0x956
11 12 13 14
OD12 — OD14
10 11 12 13
— — D12 D13 D14
— — 0 0
R/W R/W R/W R/W
Port A
15
—
14 15
D15
0 0