Gpt Output Compare 3 Data Register (Gptoc3D); Gpt Counter Register (Gptcnt) - Freescale Semiconductor ColdFire MCF52210 ColdFire MCF52211 ColdFire MCF52212 ColdFire MCF52213 Reference Manual

Field
7–4 Reserved, should be cleared.
3–0 Output compare 3 mask. Setting an OC3M bit configures the corresponding PORTTn pin to be an output. OC3Mn
OC3M makes the GPT port pin an output regardless of the data direction bit when the pin is configured for output compare
(IOSx = 1). The OC3Mn bits do not change the state of the PORTTnDDR bits. These bits are read anytime, write
anytime.
1 Corresponding PORTTn pin configured as output
0 No effect
21.6.4

GPT Output Compare 3 Data Register (GPTOC3D)

IPSBAR
Offset: 0x1A_0003 (GPTOC3D)
7
R 0
W
Reset: 0
Figure 21-5. GPT Output Compare 3 Data Register (GPTOC3D)
Field
7–4 Reserved, should be cleared.
3–0 Output compare 3 data. When a successful channel 3 output compare occurs, these bits transfer to the PORTTn
OC3D data register if the corresponding OC3Mn bits are set. These bits are read anytime, write anytime.
A successful channel 3 output compare overrides any channel 2:0 compares.
For each OC3M bit that is set, the output compare action reflects the
corresponding OC3D bit.
21.6.5

GPT Counter Register (GPTCNT)

IPSBAR
Offset: 0x1A_0004 (GPTCNT)
15 14 13
R
W
Reset 0 0
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
Table 21-6. GPTOC3M Field Descriptions
6 5
0 0
0 0
Table 21-7. GPTOC3D Field Descriptions
12 11 10
0 0 0 0
Figure 21-6. GPT Counter Register (GPTCNT)
Description
4 3
0
0 0
Description
NOTE
9 8 7 6
CNTR
0 0 0 0
General Purpose Timer Module (GPT)
Access: Supervisor read/write
2 1
OC3D
0 0
Access: Supervisor read-only
5 4 3 2
0 0 0 0
0
0
1 0
0 0
21-7