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PCI
15.2.4.7 PCI Error Data Low Capture Register (PCI_EDLCR)
PCI_EDLCR
Bit
31
30
29
Type
Reset
0
0
0
Bit
15
14
13
Type
Reset
0
0
0
PCI_EDLCR stores the data associated with the first PCI error captured. Table 15-30 shows the
PCI_EDLCR bit field.
Bits
PCI_EDR
PCI Error Data
31–0
Contains the data associated with the first detected error.
15.2.4.8 PCI Inbound Translation Address Registers 0–2 (PITAR[0–2])
PITAR0
PITAR1
PITAR2
Bit
31
30
29
Type
Reset
0
0
0
Bit
15
14
13
Type
Reset
0
0
0
PITAR[0–2] define the starting point of the corresponding inbound translation windows in the
local memory space. Table 15-31 describes the PITAR[0–2] bit fields.
Bits
—
Reserved. Write to 0 for future compatibility.
31–20
TA
Translation Address
19–0
This field contains the starting address of the inbound translated address. This 20-bit field corresponds to bits
31–12 of a 32-bit address.
15-40
PCI Error Data Low Capture Register
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
Table 15-30. PCI_EDLCR Field Descriptions
PCI Inbound Translation Address Registers 0–2
28
27
26
25
—
0
0
0
0
12
11
10
9
0
0
0
0
Table 15-31. PITAR[0–2] Field Descriptions
MSC8144E Reference Manual, Rev. 3
24
23
22
21
PCI_EDR
R/W
0
0
0
0
8
7
6
5
PCI_EDR
R/W
0
0
0
0
Description
24
23
22
21
R/W
0
0
0
0
8
7
6
5
TA
R/W
0
0
0
0
Description
Offset 0x018
20
19
18
17
0
0
0
0
4
3
2
1
0
0
0
0
Offset 0x068
Offset 0x050
Offset 0x038
20
19
18
17
TA
0
0
0
0
4
3
2
1
0
0
0
0
Freescale Semiconductor
16
0
0
0
16
0
0
0
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