Source Synchronous - Data Group - Intel 855GM Design Manual

Intel Pentium M/Celeron M Front Side Bus Design Guidelines
with nominal package lengths and that package length compensation be performed as secondary
operation.
4.1.3.3. Source Synchronous – Data Group
Robust operation of the 400-MHz, source synchronous data signals require tight skew control. For this
reason, these signals are split into matched groups as outlined in Table 4. All the signals within the same
group should be kept on the same layer of motherboard routing and should be routed to the same pad-to-
pin length within ±100 mils of the associated strobes. Only the Intel Pentium M / Intel Celeron M
processor has the package trace equalization for signals within each data and address group. The GMCH
does not have the package trace equalization for signals within each data and address group. See Table 8
for the package lengths. Please refer to Section 4.1.2.1 for trace length and package compensation
requirements. The two complementary strobe signals associated with each group should be length
matched (pad-to-pin) to each other within ± 25 mils and tuned to the average length of the data signals
(pad-to-pin) of their associated group. This will optimize setup/hold time margin.
Current simulation results provide routing guidelines using 3:1 spacing for the PSB source synchronous
data and strobe signals. This implies a minimum of 12-mil spacing (i.e. 16-mil minimum pitch) for a 4-
mil trace width. Practical cases of escape routing under the GMCH or the processor package outline and
vicinity may not even allow the implementation of 2:1 trace spacing requirements. Although every
attempt should be made to maximize the signal spacing in these areas, it is allowable to have 1:1 trace
spacing underneath the GMCH and the processor package outlines and up to 200 – 300 mils outside the
package outline. The benefits of additional spacing include increased signal quality and voltage
margining. The trace routing and length matching requirements are as follows in Section 4.1.3.1 to
Section 4.1.3.5. Note that if trace impedance can be controlled to within ± 10%, the PSB data signals
can then be routed using 2:1 spacing guidelines. The strobes, however, must still be routed with 3:1
spacing.
Table 4. Processor PSB Data Source Synchronous Signal Trace Length Mismatch Mapping
Data Group
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
NOTES:
1. Strobes of the same group should be trace length matched to each other within ±25 mil and to the average
length of their associated Data signal group.
2. Note that all length matching formulas are based on GMCH die-pad to processor pin total length per byte lane.
Package length table are provided for all signals in order to facilitate this pad to pin matching.
Table 5 lists the source synchronous data signal general routing requirements. Due to the 400-MHz,
high frequency operation of the data signals should be limited to a pin-to-pin trace length minimum of
0.50 inches and maximum of 5.5 inches.
44
DINV signal for
Signal
associated
Matching
Data Group
DINV0# ± 100 mils
DINV1# ± 100 mils
DINV2# ± 100 mils
DINV3# ± 100 mils
Data Strobes associated
With the Group
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
®
Intel 855GM/855GME Chipset Platform Design Guide
R
Strobe
Notes
Matching
± 25 mils 1,2
± 25 mils 1,2
± 25 mils 1,2
± 25 mils 1,2