Ddr So-Dimm Interface; Sodimm Decoupling Recommendation; Figure 152. Reference Voltage Level For Smvref - Intel 855GM Design Manual

R

Figure 152. Reference Voltage Level for SMVREF

10k+/- 1%
10k+/-1 %
16.6.1.2.

DDR SO-DIMM Interface

Pin Name
VREF[2:1]
VDD[33:1] Connect to VccSus2_5
VDDSPD Connect to Vcc3_3
SA[2:0] Connect to either VC3_3 or
gnd
VSS[31:1] Connect to gnd
RESET(DU)
VDDID
DU[4:1]
GND[1:0]
16.6.1.3.

SODIMM Decoupling Recommendation

Pin Name
Vcc1_25 0.1 µF
0.01 µF
Vcc2_5Sus 0.1 µF
100-150 µF
®
Intel 855GM/855GME Chipset Platform Design Guide
VccSus2_5
Configuration
Signal voltage level = VCCSus2_5 / 2.
Power must be provided during S3.
These lines are used for strapping the SPD address for each SO-DIMM.
Signal can be left as NC ("Not Connected)
Signal can be left as NC ("Not Connected)
Signal can be left as NC ("Not Connected)
Signal can be left as NC ("Not Connected)
F Qty
Place one 0.1 µF cap and one 0.01 µF close to every 4 pull-up resistors
terminated to Vcc1_25 (VTT for DDR signal termination). In S3, Vcc1_25
is powered OFF.
9 A minimum of 9 high frequency caps are recommeneded to be placed
bewteen the SO-DIMMS. A minimum of 4 low frequency caps are
4
required.
+
SMVREF
-
0.1 uF
Notes
Notes
Platform Design Checklist
GMCH
SMVREF_0
293