Signal - Intel F-Tile SDI II Agilex User Manual

D1 D3
Table 13. On-board LED Functions
LEDs
D2, D4, D6
D8
D7
D1
D3
D5
Table 14. D3-D5 LED status and its video standard on Agilex I-series SoC Dev Kit
D2, D4, D6
000
001
010
011
100
101
110
111

2.4.4. Signal

Table 15. Top Level Signals
Signal Name
clk_a_12c_fgt_p_7
clk_a_12c_fgt_p_3
clk_3a_gpio_p_2
f_gpio_00
fpga_resetn
fpga_sgpio_clk
fpga_sgpio_sync
fpga_sgpi
® ™
F-Tile SDI II Intel Agilex FPGA IP Design Example User Guide
30
D5 D7 D2 D4
Indicate the receiver video standard.
Shows the slower version of TX transceiver parallel clock.
Shows the slower version of RX transceiver parallel clock.
Illuminates when
align_locked
Illuminates when
trs_locked
Illuminates when
frame_locked
SD
HD
3G Level B 10-bit Multiplex
3G Level A 10-bit Multiplex
6G 10-bit Multiplex Type 2
6G 10-bit Multiplex Type 1
12G 10-bit Multiplex Type 2
12G 10-bit Multiplex Type 1
Direction Width
On-board Oscillators
Input 1
Input 1
Input 1
User DIP switches, pushbuttons and LEDs
Input 1
Input 1
Input 1
Input 1
Input 1
2. Design Example Detailed Description
D6 D8
Functions
signal is asserted.
signal is asserted
signal is asserted.
Video standard
Description
156.25 Mhz dedicated transceiver reference clock.
148.5 Mhz dedicated transceiver reference clock.
148.5 Mhz GPIO clock.
Pushbutton to powerdown LMK03328 after switching the
jumper settings.
Global reset
SGPIO slave signals. These groups of signals connect to
the MAX device to control the on-board LEDs and DIPSW.
710496 | 2022.01.28
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